Chao-Hsuan Huang

According to our database, Chao-Hsuan Huang authored at least 3 papers between 2019 and 2020.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2020

Mitigating the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration.

Chao-Hsuan Huang, Ishan G. Thakkar

CoRR, 2020

Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration.

Chao-Hsuan Huang, Ishan G. Thakkar

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019

Mitigating Write Disturbance in Phase Change Memory Architectures.

Chao-Hsuan Huang, Ishan G. Thakkar

Proceedings of the 2019 International Conference on Compliers, 2019