Charanya K. Rao

According to our database¹, Charanya K. Rao authored at least 2 papers in 2025.

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2025

ASIC Design Flow Using Simulink and Cadence Digital IC Design Tools.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025

Digital IC Design of a 45nm CMOS Chua Encryption Architecture for Resource Limited Devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025