Christos Pavlatos

Orcid: 0000-0002-5057-1720

According to our database1, Christos Pavlatos authored at least 17 papers between 2004 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2022
Multi-output, multi-level, multi-gate design using non-linear programming.
Int. J. Circuit Theory Appl., 2022

An Intelligent Grammar-Based Platform for RNA H-type Pseudoknot Prediction.
Proceedings of the Artificial Intelligence Applications and Innovations. AIAI 2022 IFIP WG 12.5 International Workshops, 2022

2020
Logic Design Using Modules and Nonlinear Integer Programming.
J. Circuits Syst. Comput., 2020

2017
Hardware Inexact Grammar Parser.
Int. J. Pattern Recognit. Artif. Intell., 2017

2016
Parallel Hardware Stochastic Context-Free Parsers.
Int. J. Pattern Recognit. Artif. Intell., 2016

A General Purpose Branch and Bound Parallel Algorithm.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

2011
Effectiveness of Heuristic Based Approach on the Performance of Indexing and Clustering of High Dimensional Data.
J. Inf. Knowl. Manag., 2011

2010
A platform for the automatic generation of attribute evaluation hardware systems.
Comput. Lang. Syst. Struct., 2010

2009
Efficient reconfigurable embedded parsers.
Comput. Lang. Syst. Struct., 2009

A Formal Method for Rapid SoC Prototyping.
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

TELIOS: A Tool for the Automatic Generation of Logic Programming Machines.
Proceedings of the Artificial Intelligence Applications and Innovations III, 2009

2007
A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Hardware Natural Language Interface.
Proceedings of the Artificial Intelligence and Innovations 2007: from Theory to Applications, 2007

2006
An Efficient Hardware Implementation for AI Applications.
Proceedings of the Advances in Artificial Intelligence, 4th Helenic Conference on AI, 2006

2005
An Embedded Microprocessor for Intelligent Control.
J. Intell. Robotic Syst., 2005

2004
Knowledge Representation Using a Modified Earley's Algorithm.
Proceedings of the Methods and Applications of Artificial Intelligence, 2004

A hardware extension of the RISC microprocessor for Attribute Grammar evaluation.
Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004


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