Davide Rossi
Orcid: 0000-0002-0651-5393
According to our database1,
Davide Rossi
authored at least 221 papers
between 1996 and 2024.
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Bibliography
2024
ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation.
Int. J. Parallel Program., April, 2024
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing.
IEEE J. Solid State Circuits, January, 2024
Assessing the Performance of OpenTitan as Cryptographic Accelerator in Secure Open-Hardware System-on-Chips.
CoRR, 2024
2023
RedMule: A mixed-precision matrix-matrix operation engine for flexible and energy-efficient on-chip linear algebra and TinyML training acceleration.
Future Gener. Comput. Syst., December, 2023
CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration.
IEEE Trans. Very Large Scale Integr. Syst., November, 2023
Graphene-Based Wireless Agile Interconnects for Massive Heterogeneous Multi-Chip Processors.
IEEE Wirel. Commun., August, 2023
IEEE Trans. Very Large Scale Integr. Syst., April, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine.
CoRR, 2023
CoRR, 2023
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing.
CoRR, 2023
Echoes: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays.
CoRR, 2023
DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training.
CoRR, 2023
Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space.
CoRR, 2023
A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
ECHOES: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I<sup>2</sup>S DSP for Flexible Data Acquisition from Microphone Arrays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Cyber Security aboard Micro Aerial Vehicles: An OpenTitan-based Visual Communication Use Case.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the 35th IEEE Hot Chips Symposium, 2023
Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Processing in 16nm CMOS.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Reducing Load-Use Dependency-Induced Performance Penalty in the Open-Source RISC-V CVA6 CPU.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
TransLib: A Library to Explore Transprecision Floating-Point Arithmetic on Multi-Core IoT End-Nodes.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics.
IEEE Trans. Parallel Distributed Syst., 2022
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
IEEE J. Solid State Circuits, 2022
A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
WISE: A Semantic and Interoperable Web of Things Architecture for Smart Environments.
Proceedings of the 8th IEEE World Forum on Internet of Things, 2022
ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022
Geographic Diversity in Public Code Contributions: An Exploratory Large-Scale Study Over 50 Years.
Proceedings of the 19th IEEE/ACM International Conference on Mining Software Repositories, 2022
Proceedings of the Leveraging Applications of Formal Methods, Verification and Validation. Verification Principles, 2022
Worldwide Gender Differences in Public Code Contributions and how they have been affected by the COVID-19 pandemic.
Proceedings of the 44th IEEE/ACM International Conference on Software Engineering: Software Engineering in Society ICSE (SEIS) 2022, 2022
Kraken: A Direct Event/Frame-Based Multi-sensor Fusion SoC for Ultra-Efficient Visual Processing in Nano-UAVs.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation.
IEEE Trans. Very Large Scale Integr. Syst., 2021
A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters.
IEEE Trans. Parallel Distributed Syst., 2021
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes.
IEEE Trans. Emerg. Top. Comput., 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Computers, 2021
Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
CoRR, 2021
A Fully-Integrated 5mW, 0.8Gbps Energy-Efficient Chip-to-Chip Data Link for Ultra-Low-Power IoT End-Nodes in 65-nm CMOS.
CoRR, 2021
Hardware-In-The Loop Emulation for Agile Co-Design of Parallel Ultra-Low Power IoT Processors.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode.
Proceedings of the 47th ESSCIRC 2021, 2021
Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH).
Proceedings of the CF '21: Computing Frontiers Conference, 2021
Proceedings of the Architecture of Computing Systems - 34th International Conference, 2021
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
Always-On 674μ W@4GOP/s Error Resilient Binary Neural Networks With Aggressive SRAM Voltage Scaling on a 22-nm IoT End-Node.
IEEE Trans. Circuits Syst., 2020
Modular Design and Optimization of Biomedical Applications for Ultralow Power Heterogeneous Platforms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Microprocess. Microsystems, 2020
Performance-aware predictive-model-based on-chip body-bias regulation strategy for an ULP multi-core cluster in 28 nm UTBB FD-SOI.
Integr., 2020
Int. J. Softw. Eng. Knowl. Eng., 2020
Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge.
IEEE Embed. Syst. Lett., 2020
Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices.
IEEE Des. Test, 2020
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes.
CoRR, 2020
Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors.
CoRR, 2020
CoRR, 2020
Performance-Aware Predictive-Model-Based On-Chip Body-Bias Regulation Strategy for an ULP Multi-Core Cluster in 28nm UTBB FD-SOI.
CoRR, 2020
Always-On 674uW @ 4GOP/s Error Resilient Binary Neural Networks with Aggressive SRAM Voltage Scaling on a 22nm IoT End-Node.
CoRR, 2020
IEEE Access, 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the GoodTechs '20: 6th EAI International Conference on Smart Objects and Technologies for Social Good, 2020
TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Energy-Efficient Two-level Instruction Cache Design for an Ultra-Low-Power Multi-core Cluster.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020
Neuro-PULP: A Paradigm Shift Towards Fully Programmable Platforms for Neural Interfaces.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
BioWolf: A Sub-10-mW 8-Channel Advanced Brain-Computer Interface Platform With a Nine-Core Processor and BLE Connectivity.
IEEE Trans. Biomed. Circuits Syst., 2019
Online Learning and Classification of EMG-Based Gestures on a Parallel Ultra-Low Power Platform Using Hyperdimensional Computing.
IEEE Trans. Biomed. Circuits Syst., 2019
An architecture for context-aware reactive systems based on run-time semantic models.
PeerJ Prepr., 2019
Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing.
IEEE J. Solid State Circuits, 2019
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
PULP-NN: Accelerating Quantized Neural Networks on Parallel Ultra-Low-Power RISC-V Processors.
CoRR, 2019
Proceedings of the 31st International Conference on Software Engineering and Knowledge Engineering, 2019
An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks.
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019
Proceedings of the IEEE International Symposium on Software Reliability Engineering Workshops, 2019
PULP-NN: A Computing Library for Quantized Neural Network inference at the edge on RISC-V Based Parallel Ultra Low Power Clusters.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 20th IEEE International Conference on High Performance Switching and Routing, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Hardware-Accelerated Energy-Efficient Synchronization and Communication for Ultra-Low-Power Tightly Coupled Clusters.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
DORY: Lightweight memory hierarchy management for deep NN inference on IoT endnodes: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019
2018
NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs.
ACM Trans. Reconfigurable Technol. Syst., 2018
IEEE Trans. Parallel Distributed Syst., 2018
IEEE Trans. Multi Scale Comput. Syst., 2018
A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Online Inf. Rev., 2018
Power mitigation of a heterogeneous multicore architecture on FPGA/ASIC by DFS/DVFS techniques.
Microprocess. Microsystems, 2018
Capturing and managing knowledge using social software and semantic web technologies.
Inf. Sci., 2018
A sensor fusion approach for drowsiness detection in wearable ultra-low-power systems.
Inf. Fusion, 2018
Proceedings of the Web Information Systems and Technologies, 2018
Microservices: The Chain of Calls and the Radar of Freedom.
Proceedings of the 14th International Conference on Web Information Systems and Technologies, 2018
Proceedings of the 33rd Annual ACM Symposium on Applied Computing, 2018
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018
Hyperdrive: A Systolically Scalable Binary-Weight CNN Inference Engine for mW IoT End-Nodes.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Live Demonstration: Body-Bias Based Performance Monitoring and Compensation for a Near-Threshold Multi-Core Cluster in 28nm FD-SOI Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data Analytics.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Compressed Sensing Based Seizure Detection for an Ultra Low Power Multi-core Architecture.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018
Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Energy proportionality in near-threshold computing servers and cloud data centers: Consolidating or Not?
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
PULP-HD: accelerating brain-inspired high-dimensional computing on a parallel ultra-low power platform.
Proceedings of the 55th Annual Design Automation Conference, 2018
Always-ON visual node with a hardware-software event-based binarized neural network inference engine.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE Micro, 2017
Increasing the energy efficiency of microcontroller platforms with low-design margin co-processors.
Microprocess. Microsystems, 2017
IEEE Internet Things J., 2017
A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors.
IEEE Des. Test, 2017
Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
A wearable EEG-based drowsiness detection system with blink duration and alpha waves analysis.
Proceedings of the 8th International IEEE/EMBS Conference on Neural Engineering, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision.
J. Signal Process. Syst., 2016
Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement.
ACM Trans. Design Autom. Electr. Syst., 2016
Proceedings of the 25th IEEE International Conference on Enabling Technologies: Infrastructure for Collaborative Enterprises, 2016
Proceedings of the 12th International Conference on Web Information Systems and Technologies, 2016
Proceedings of 5th International Conference in Software Engineering for Defence Applications, 2016
Proceedings of the 2nd IEEE International Forum on Research and Technologies for Society and Industry Leveraging a better tomorrow, 2016
YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Smart Cities Conference, 2016
Always-on motion detection with application-level error control on a near-threshold approximate computing platform.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
A 2 MS/s 10A Hall current sensor SoC with digital compressive sensing encoder in 0.16 µm BCD.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Enabling the heterogeneous accelerator model on ultra-low power microcontroller platforms.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory Cube.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Synergistic Architecture and Programming Model Support for Approximate Micropower Computing.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015
Reducing energy consumption in microcontroller-based platforms with low design margin co-processors.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Exploring multi-banked shared-L1 program cache on ultra-low power, tightly coupled processor clusters.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015
Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Multicore Signal Processing Platform With Heterogeneous Configurable Hardware Accelerators.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Sci. Comput. Program., 2014
Proceedings of the 2014 IEEE 23rd International WETICE Conference, 2014
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Customizing an open source processor to fit in an ultra-low power cluster with a shared L1 memory.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Hybrid memory architecture for voltage scaling in ultra-low power multi-core biomedical processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Computing Frontiers Conference, CF'14, 2014
2013
Application Space Exploration of a Heterogeneous Run-Time Configurable Digital Signal Processor.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Promoting Best Practice Sharing within Organizations.
Proceedings of the WEBIST 2013, 2013
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
2012
PhD thesis, 2012
Proceedings of the Coordination Models and Languages - 14th International Conference, 2012
2011
Int. J. Parallel Program., 2011
2010
J. Softw. Maintenance Res. Pract., 2010
IEEE J. Solid State Circuits, 2010
A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations.
J. Syst. Archit., 2010
2009
An Executable Language/Enactment Engine Approach for Designing and Architecting Process-Aware Web Applications.
Int. J. E Bus. Res., 2009
Proceedings of the Workshop on Adaptation and Personalization for Web 2.0, 2009
Proceedings of the 2009 ACM Symposium on Applied Computing (SAC), 2009
Proceedings of the 2009 ACM Symposium on Applied Computing (SAC), 2009
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009
RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009
A heterogeneous digital signal processor implementation for dynamically reconfigurable computing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
Design space exploration of an open-source, IP-reusable, scalable floating-point engine for embedded applications.
J. Syst. Archit., 2008
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008
Implementation of a floating-point matrix-vector multiplication on a reconfigurable architecture.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Proceedings of the Third International Conference on Software Engineering Advances, 2008
Proceedings of the Business Process Management Workshops, 2008
2007
IEEE Trans. Software Eng., 2007
Using a process modeling language for the design and implementation of process-driven applications.
Proceedings of the Second International Conference on Software Engineering Advances (ICSEA 2007), 2007
EGO: an E-Games Orchestration Platform.
Proceedings of the GAMEON'2007, 2007
2006
2005
Proceedings of the 2005 ACM Symposium on Applied Computing (SAC), 2005
Proceedings of the Fourth IEEE International Symposium on Network Computing and Applications (NCA 2005), 2005
Proceedings of the 2005 International Symposium on System-on-Chip, 2005
Proceedings of the Networking, 2005
Proceedings of the Joint International Conference on Autonomic and Autonomous Systems 2005 / International Conference on Networking and Services 2005, 2005
Proceedings of the Coordination Models and Languages, 7th International Conference, 2005
2004
Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004
2002
New Rev. Hypermedia Multim., 2002
Proceedings of the 2002 ACM Symposium on Document Engineering, 2002
2001
Interact. Comput., 2001
WebCluster: A Web-Accessible Cluster Computing System Based on Coordination and Mobility.
Proceedings of the Parallel Computing Technologies, 2001
Tuple-based Technologies for Coordination.
Proceedings of the Coordination of Internet Agents: Models, Technologies, and Applications, 2001
1999
Internet-Based Coordination Environments and Document-Based Applications: A Case Study.
Proceedings of the Coordination Languages and Models, Third International Conference, 1999
Proceedings of the Advances in Distributed Systems, 1999
1998
IEEE Trans. Software Eng., 1998
Proceedings of the 7th Workshop on Enabling Technologies (WETICE '98), 1998
Proceedings of the 1998 ACM symposium on Applied Computing, 1998
1997
Proceedings of the 6th Workshop on Enabling Technologies (WET-ICE '97), 1997
Coordinating Java Agents for Financial Applications on the WWW.
Proceedings of the Second International Conference on the Practical Application of Intelligent Agents and Multi-Agent Technology, 1997
Proceedings of the Third International Symposium on Autonomous Decentralized Systems, 1997
1996
Proceedings of the 5th Workshop on Enabling Technologies, 1996
Proceedings of the Mobile Object Systems, 1996