Davide Rossi

According to our database1, Davide Rossi authored at least 138 papers between 1996 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A Fully Programmable eFPGA-Augmented SoC for Smart Power Applications.
IEEE Trans. on Circuits and Systems, 2020

A custom processor for protocol-independent packet parsing.
Microprocess. Microsystems, 2020

2019
An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

BioWolf: A Sub-10-mW 8-Channel Advanced Brain-Computer Interface Platform With a Nine-Core Processor and BLE Connectivity.
IEEE Trans. Biomed. Circuits and Systems, 2019

Online Learning and Classification of EMG-Based Gestures on a Parallel Ultra-Low Power Platform Using Hyperdimensional Computing.
IEEE Trans. Biomed. Circuits and Systems, 2019

An architecture for context-aware reactive systems based on run-time semantic models.
PeerJ PrePrints, 2019

Integrating Semantic Run-Time Modelsfor Adaptive Software Systems.
J. Web Eng., 2019

Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing.
J. Solid-State Circuits, 2019

Hyperdrive: A Multi-Chip Systolically Scalable Binary-Weight CNN Inference Engine.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

PULP-NN: Accelerating Quantized Neural Networks on Parallel Ultra-Low-Power RISC-V Processors.
CoRR, 2019

Context-aware Reactive Systems based on Runtime Semantic Models (S).
Proceedings of the 31st International Conference on Software Engineering and Knowledge Engineering, 2019

An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks.
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

Resilient Reactive Systems Based on Runtime Semantic Models.
Proceedings of the IEEE International Symposium on Software Reliability Engineering Workshops, 2019

PULP-NN: A Computing Library for Quantized Neural Network inference at the edge on RISC-V Based Parallel Ultra Low Power Clusters.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

A PULP-based Parallel Power Controller for Future Exascale Systems.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Reducing Crossbar Costs in the Match-Action Pipeline.
Proceedings of the 20th IEEE International Conference on High Performance Switching and Routing, 2019

Design and Evaluation of SmallFloat SIMD extensions to the RISC-V ISA.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Hardware-Accelerated Energy-Efficient Synchronization and Communication for Ultra-Low-Power Tightly Coupled Clusters.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

DORY: Lightweight memory hierarchy management for deep NN inference on IoT endnodes: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019

2018
NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs.
TRETS, 2018

Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes.
IEEE Trans. Parallel Distrib. Syst., 2018

The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores.
IEEE Trans. Multi-Scale Computing Systems, 2018

A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing.
IEEE Trans. on Circuits and Systems, 2018

Synergistic HW/SW Approximation Techniques for Ultralow-Power Parallel Computing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Supporting authors in documenting and sharing operative knowledge.
Online Information Review, 2018

Power mitigation of a heterogeneous multicore architecture on FPGA/ASIC by DFS/DVFS techniques.
Microprocess. Microsystems, 2018

Capturing and managing knowledge using social software and semantic web technologies.
Inf. Sci., 2018

A sensor fusion approach for drowsiness detection in wearable ultra-low-power systems.
Inf. Fusion, 2018

Consistency and Availability in Microservice Architectures.
Proceedings of the Web Information Systems and Technologies, 2018

Microservices: The Chain of Calls and the Radar of Freedom.
Proceedings of the 14th International Conference on Web Information Systems and Technologies, 2018

Dynamic high-level requirements in self-adaptive systems.
Proceedings of the 33rd Annual ACM Symposium on Applied Computing, 2018

Low-latency Packet Parsing in Software Defined Networks.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

Hyperdrive: A Systolically Scalable Binary-Weight CNN Inference Engine for mW IoT End-Nodes.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Live Demonstration: Body-Bias Based Performance Monitoring and Compensation for a Near-Threshold Multi-Core Cluster in 28nm FD-SOI Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data Analytics.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Compressed Sensing Based Seizure Detection for an Ultra Low Power Multi-core Architecture.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018

Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

A transprecision floating-point platform for ultra-low power computing.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Energy proportionality in near-threshold computing servers and cloud data centers: Consolidating or Not?
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

PULP-HD: accelerating brain-inspired high-dimensional computing on a parallel ultra-low power platform.
Proceedings of the 55th Annual Design Automation Conference, 2018

Always-ON visual node with a hardware-software event-based binarized neural network inference engine.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

An Explicitly Parallel Architecture for Packet Parsing in Software Defined Networks.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

GAP-8: A RISC-V SoC for AI at the Edge of the IoT.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017
Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices.
IEEE Trans. VLSI Syst., 2017

Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube.
IEEE Trans. VLSI Syst., 2017

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics.
IEEE Trans. on Circuits and Systems, 2017

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster.
IEEE Micro, 2017

Increasing the energy efficiency of microcontroller platforms with low-design margin co-processors.
Microprocess. Microsystems, 2017

A Sub-mW IoT-Endnode for Always-On Visual Monitoring and Smart Triggering.
IEEE Internet of Things Journal, 2017

A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors.
IEEE Design & Test, 2017

Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

μDMA: An autonomous I/O subsystem for IoT end-nodes.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

A wearable EEG-based drowsiness detection system with blink duration and alpha waves analysis.
Proceedings of the 8th International IEEE/EMBS Conference on Neural Engineering, 2017

A 142MOPS/mW integrated programmable array accelerator for smart visual processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Analyzing and predicting concurrency bugs in open source systems.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Efficient mapping of CDFG onto coarse-grained reconfigurable array architectures.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision.
Signal Processing Systems, 2016

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement.
ACM Trans. Design Autom. Electr. Syst., 2016

Semantic Run-Time Models for Self-Adaptive Systems: A Case Study.
Proceedings of the 25th IEEE International Conference on Enabling Technologies: Infrastructure for Collaborative Enterprises, 2016

UML-based Model-Driven REST API Development.
Proceedings of the 12th International Conference on Web Information Systems and Technologies, 2016

An Initial Investigation of Concurrency Bugs in Open Source Systems.
Proceedings of 5th International Conference in Software Engineering for Defence Applications, 2016

An application of semantic technologies to self adaptations.
Proceedings of the 2nd IEEE International Forum on Research and Technologies for Society and Industry Leveraging a better tomorrow, 2016

YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Energy-efficient design of an always-on smart visual trigger.
Proceedings of the IEEE International Smart Cities Conference, 2016

Always-on motion detection with application-level error control on a near-threshold approximate computing platform.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

A 2 MS/s 10A Hall current sensor SoC with digital compressive sensing encoder in 0.16 µm BCD.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Towards near-threshold server processors.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Enabling the heterogeneous accelerator model on ultra-low power microcontroller platforms.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

Scalable EEG seizure detection on an ultra low power multi-core architecture.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory Cube.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

2015
A Modular Shared L2 Memory Design for 3-D Integration.
IEEE Trans. VLSI Syst., 2015

Editorial.
J. Web Eng., 2015

Synergistic Architecture and Programming Model Support for Approximate Micropower Computing.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

PULP: A parallel ultra low power platform for next generation IoT applications.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

Reducing energy consumption in microcontroller-based platforms with low design margin co-processors.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

High performance AXI-4.0 based interconnect for extensible smart memory cubes.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Exploring multi-banked shared-L1 program cache on ultra-low power, tightly coupled processor clusters.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Multicore Signal Processing Platform With Heterogeneous Configurable Hardware Accelerators.
IEEE Trans. VLSI Syst., 2014

Web Technologies: Selected & extended papers from WT ACM SAC 2012.
Sci. Comput. Program., 2014

Exploiting Semantic Knowledge in Know Best.
Proceedings of the 2014 IEEE 23rd International WETICE Conference, 2014

Energy-efficient vision on the PULP platform for ultra-low power parallel computing.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Customizing an open source processor to fit in an ultra-low power cluster with a shared L1 memory.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Hybrid memory architecture for voltage scaling in ultra-low power multi-core biomedical processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters.
Proceedings of the Computing Frontiers Conference, CF'14, 2014

2013
Application Space Exploration of a Heterogeneous Run-Time Configurable Digital Signal Processor.
IEEE Trans. VLSI Syst., 2013

Promoting Best Practice Sharing within Organizations.
Proceedings of the WEBIST 2013, 2013

A variation tolerant architecture for ultra low power multi-processor cluster.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Exploiting body biasing for leakage reduction: A case study.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

2012
Multi Processor Systems On Chip with Configurable Hardware Acceleration.
PhD thesis, 2012

A Social Software-Based Coordination Platform - Tool Paper.
Proceedings of the Coordination Models and Languages - 14th International Conference, 2012

2011
The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform.
International Journal of Parallel Programming, 2011

2010
Combining BPM and social software: contradiction or chance?
Journal of Software Maintenance, 2010

Editorial.
J. Web Eng., 2010

A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing.
J. Solid-State Circuits, 2010

A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations.
J. Syst. Archit., 2010

2009
An Executable Language/Enactment Engine Approach for Designing and Architecting Process-Aware Web Applications.
IJEBR, 2009

Customized Edit Interfaces for Wikis via Semantic Annotations.
Proceedings of the Workshop on Adaptation and Personalization for Web 2.0, 2009

Simulating business processes with EPML.SIM.
Proceedings of the 2009 ACM Symposium on Applied Computing (SAC), 2009

Where are your manners?: Sharing best community practices in the web 2.0.
Proceedings of the 2009 ACM Symposium on Applied Computing (SAC), 2009

A heterogeneous digital signal processor implementation for dynamically reconfigurable computing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Design space exploration of an open-source, IP-reusable, scalable floating-point engine for embedded applications.
J. Syst. Archit., 2008

Designing and architecting process-aware Web applications with EPML.
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

EPML: an executable process modeling language for process-aware applications.
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

Implementation of a floating-point matrix-vector multiplication on a reconfigurable architecture.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

On the Effectiveness of Manual and Automatic Unit Test Generation.
Proceedings of the Third International Conference on Software Engineering Advances, 2008

Workflow Enactment in a Social Software Environment.
Proceedings of the Business Process Management Workshops, 2008

2007
SLA-Driven Clustering of QoS-Aware Application Servers.
IEEE Trans. Software Eng., 2007

Using a process modeling language for the design and implementation of process-driven applications.
Proceedings of the Second International Conference on Software Engineering Advances (ICSEA 2007), 2007

EGO: an E-Games Orchestration Platform.
Proceedings of the GAMEON'2007, 2007

2006
X-Folders: documents on the move.
Concurrency and Computation: Practice and Experience, 2006

2005
An OWL-S based approach to express grid services coordination.
Proceedings of the 2005 ACM Symposium on Applied Computing (SAC), 2005

Experimental Evaluation of a QoS-aware Application Server.
Proceedings of the Fourth IEEE International Symposium on Network Computing and Applications (NCA 2005), 2005

Analyzing Performance Data Exchange in Content Delivery Networks.
Proceedings of the Networking, 2005

Analyzing the Impact of Components Replication in High Available J2EE Clusters.
Proceedings of the Joint International Conference on Autonomic and Autonomous Systems 2005 / International Conference on Networking and Services 2005, 2005

Transactional Aspects in Semantic Based Discovery of Services.
Proceedings of the Coordination Models and Languages, 7th International Conference, 2005

2004
Orchestrating document-based workflows with X-Folders.
Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004

2002
XlinkProxy: external linkbases wih Xlink (Technical Note).
The New Review of Hypermedia and Multimedia, 2002

XLinkProxy: external linkbases with XLink.
Proceedings of the 2002 ACM Symposium on Document Engineering, 2002

2001
Designing a document-centric coordination application over the Internet.
Interacting with Computers, 2001

WebCluster: A Web-Accessible Cluster Computing System Based on Coordination and Mobility.
Proceedings of the Parallel Computing Technologies, 2001

Tuple-based Technologies for Coordination.
Proceedings of the Coordination of Internet Agents: Models, Technologies, and Applications, 2001

1999
Internet-Based Coordination Environments and Document-Based Applications: A Case Study.
Proceedings of the Coordination Languages and Models, Third International Conference, 1999

Mobility and Coordination for Distributed Java Applications.
Proceedings of the Advances in Distributed Systems, 1999

1998
Coordinating Java Agents over the WWW.
World Wide Web, 1998

Coordinating Multiagent Aplications on the WWW: A Reference Architecture.
IEEE Trans. Software Eng., 1998

The World Wide Web as a Place to Work in.
Proceedings of the 7th Workshop on Enabling Technologies (WETICE '98), 1998

Coordinating distributed applets with Shade/Java.
Proceedings of the 1998 ACM symposium on Applied Computing, 1998

1997
A Multi-Agent Process Centered Environment Integrated with the WWW.
Proceedings of the 6th Workshop on Enabling Technologies (WET-ICE '97), 1997

Redesigning the Web: from passive pages to coordinated agents in PageSpaces.
Proceedings of the Third International Symposium on Autonomous Decentralized Systems, 1997

1996
Coordination technology for the WWW.
Proceedings of the 5th Workshop on Enabling Technologies, 1996

Jada - Coordination and Communication for Java Agents.
Proceedings of the Mobile Object Systems, 1996


  Loading...