Dries Vercaemer

Orcid: 0000-0003-2931-1104

According to our database1, Dries Vercaemer authored at least 4 papers between 2016 and 2019.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Low-Pass Filtering SC-DAC for Reduced Jitter and Slewing Requirements on CTSDMs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
Experimental results on PWM linearization of a VCO-ADC with 3rd order noise shaping.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Passive Loop Filter Assistance for CTSDMs.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

2016
Analyzing the Effect of Clock Jitter on Self-Oscillating Sigma Delta Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016


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