Dunbo Zhang

Orcid: 0009-0001-8854-4752

According to our database1, Dunbo Zhang authored at least 7 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Extension VM: Interleaved Data Layout in Vector Memory.
ACM Trans. Archit. Code Optim., March, 2024

2022
Compressed page walk cache.
Frontiers Comput. Sci., 2022

2021
Reducing TLB Miss Penalty on GPUs via Unified Multi-level PWB and PWC.
Proceedings of the 12th International Symposium on Parallel Architectures, 2021

A Multi-precision Quantized Super-Resolution Model Framework.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2021

Multi-level PWB and PWC for Reducing TLB Miss Overheads on GPUs.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2021

2020
A Multi-model Super-Resolution Training and Reconstruction Framework.
Proceedings of the Network and Parallel Computing, 2020

A Unified Page Walk Buffer and Page Walk Cache.
Proceedings of the IEEE International Conference on Parallel & Distributed Processing with Applications, 2020


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