Enver Cavus

According to our database1, Enver Cavus authored at least 21 papers between 2001 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2022
Self calibrated cooler-less microbolometer readout architecture.
Integr., 2022

2021
Coded Faster-than-Nyquist Signaling for Short Packet Communications.
Proceedings of the 32nd IEEE Annual International Symposium on Personal, 2021

Vehicle Detection in Aerial Imaginary using a Miniature CNN Architecture.
Proceedings of the International Conference on INnovations in Intelligent SysTems and Applications, 2021

2020
Analysis and FPGA Implementation of Zero-Forcing Receive Beamforming with Signal Space Diversity under Different Interleaving Techniques.
J. Circuits Syst. Comput., 2020

Low-Complexity MIMO MMSE Receiver with Performance Enhancement via Coordinate Interleaving.
J. Circuits Syst. Comput., 2020

A Novel Current-Controlled Oscillator-Based Low-Supply-Voltage Microbolometer Readout Architecture.
J. Circuits Syst. Comput., 2020

Polar Coded Faster-than-Nyquist (FTN) Signaling with Symbol-by-Symbol Detection.
Proceedings of the 2020 IEEE Wireless Communications and Networking Conference, 2020

2019
FPGA Implementation of Synchronization Techniques used in OFDM Systems.
Proceedings of the 27th Signal Processing and Communications Applications Conference, 2019

2018
FPGA implementation of MMSE channel estimation algorithm using system generator.
Proceedings of the 26th Signal Processing and Communications Applications Conference, 2018

Baseband implementation of high speed communication system on FPGA.
Proceedings of the 26th Signal Processing and Communications Applications Conference, 2018

FPGA implementation of symbol timing synchronization for OFDM systems.
Proceedings of the 26th Signal Processing and Communications Applications Conference, 2018

2017
Design of frequency upconversion and downconversion blocks for 240 GHz communication systems.
Proceedings of the 25th Signal Processing and Communications Applications Conference, 2017

FPGA implementation of layered low density parity check error correction codes.
Proceedings of the 25th Signal Processing and Communications Applications Conference, 2017

2016
FPGA implementation of AWGN noise generator using Box-Muller method.
Proceedings of the 24th Signal Processing and Communication Application Conference, 2016

Parallelizing LDPC Decoding Using OpenMP on Multicore Digital Signal Processors.
Proceedings of the 45th International Conference on Parallel Processing Workshops, 2016

2015
An EG-LDPC Based 2-Dimensional Error Correcting Code for Mitigating MBUs of SRAM Memories.
Proceedings of the 12th FPGAworld Conference 2015, 2015

2009
Low BER performance estimation of LDPC codes via application of importance sampling to trapping sets.
IEEE Trans. Commun., 2009

2006
A very low-complexity space-time block decoder (STBD) ASIC for wireless systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

An IS Simulation Technique for Very Low BER Performance Evaluation of LDPC Codes.
Proceedings of IEEE International Conference on Communications, 2006

2005
A performance improvement and error floor avoidance technique for belief propagation decoding of LDPC codes.
Proceedings of the IEEE 16th International Symposium on Personal, 2005

2001
A computationally efficient algorithm for space-time block decoding.
Proceedings of the IEEE International Conference on Communications, 2001


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