Ernst G. Bernard

According to our database1, Ernst G. Bernard authored at least 8 papers between 1991 and 1996.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

1996
Efficient Fault Locations for Globally Controlled and Comparison-Based Multistage Interconnection Networks.
IEEE Trans. Computers, 1996

Built-in self test architectures for multistage interconnection networks.
Proceedings of the 1996 European Design and Test Conference, 1996

1994
A New Retiming Algorithm for Circuit Design.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Fault Location in Multistage Interconnection Networks with Global and Distributed Control.
Proceedings of the 8th International Symposium on Parallel Processing, 1994

1993
Block Sequential CORDIC Architectures.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1992
A pipeline architecture for modified higher radix FFT.
Proceedings of the 1992 IEEE International Conference on Acoustics, 1992

On partitioning of multistage algorithms and design of intermediate memories.
Proceedings of the Application Specific Array Processors, 1992

1991
Sorting on defective VLSI-arrays.
Integr., 1991


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