Fedor Pikus

According to our database1, Fedor Pikus authored at least 3 papers between 2009 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2012
Parametric Hierarchy Recovery in Layout Extracted Netlists.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

2010
A framework for logic-aware layout analysis.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009
Use of lithography simulation for the calibration of equation-based design rule checks.
Proceedings of the 46th Design Automation Conference, 2009


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