Florian Enescu

Orcid: 0000-0002-9532-2568

According to our database1, Florian Enescu authored at least 25 papers between 2005 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Logic Synthesis from Polynomials with Coefficients in the Field of Rationals.
Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023

2021
Algebraic Techniques for Rectification of Finite Field Circuits.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

Word-Level Multi-Fix Rectifiability of Finite Field Arithmetic Circuits.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Rectification of Integer Arithmetic Circuits using Computer Algebra Techniques.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2019
Computing the invariants of intersection algebras of principal monomial ideals.
Int. J. Algebra Comput., 2019

Exploring Algebraic Interpolants for Rectification of Finite Field Arithmetic Circuits with Gröbner Bases.
Proceedings of the 24th IEEE European Test Symposium, 2019

2018
Rectification of Arithmetic Circuits with Craig Interpolants in Finite Fields.
Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018

On the Rectifiability of Arithmetic Circuits using Craig Interpolants in Finite Fields.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Post-Verification Debugging and Rectification of Finite Field Arithmetic Circuits using Computer Algebra Techniques.
Proceedings of the 2018 Formal Methods in Computer Aided Design, 2018

2016
Efficient Symbolic Computation for Word-Level Abstraction From Combinational Circuits for Verification Over Finite Fields.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Word-level traversal of finite state machines using algebraic geometry.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

Finding Unsatisfiable Cores of a Set of Polynomials Using the Gröbner Basis Algorithm.
Proceedings of the Principles and Practice of Constraint Programming, 2016

2015
Formal verification of sequential Galois field arithmetic circuits using algebraic geometry.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Equivalence Verification of Large Galois Field Arithmetic Circuits using Word-Level Abstraction via Gröbner Bases.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Arithmetic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2012
Efficient Gröbner basis reductions for formal verification of galois field multipliers.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Verification of composite Galois field multipliers over GF ((2<sup>m</sup>)<sup>n</sup>) using computer algebra techniques.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

2008
Simulation Bounds for Equivalence Verification of Polynomial Datapaths Using Finite Ring Algebra.
IEEE Trans. Very Large Scale Integr. Syst., 2008

2007
Equivalence Verification of Polynomial Datapaths Using Ideal Membership Testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Optimization of Arithmetic Datapaths with Finite Word-Length Operands.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands.
Proceedings of the Formal Methods in Computer-Aided Design, 6th International Conference, 2006

Equivalence verification of arithmetic datapaths with multiple word-length operands.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Exploiting Vanishing Polynomials for Equivalence Veri.cation of Fixed-Size Arithmetic Datapaths.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005


  Loading...