Gaofeng Jin

According to our database, Gaofeng Jin authored at least 6 papers between 2020 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A Low-Jitter Fractional-N LC-PLL With a 1/4 DTC-Range-Reduction Technique.

Gaofeng Jin, Fei Feng, Yan Chen, Hanli Liu, Xiang Gao

IEEE Solid State Circuits Lett., 2025

A Dual-Path SPD/PFD PLL With PVT-Insensitive Loop Bandwidth.

Yan Chen, Gaofeng Jin, Haojie Xu, Yu Cui, Lei Zeng, Xiang Gao

IEEE Solid State Circuits Lett., 2025

2024

A Fractional-N Sampling PLL With a Merged Constant-Slope DTC and Sampling PD.

Gaofeng Jin, Fei Feng, Wen Chen, Yiyang Shu, Xun Luo, Xiang Gao

IEEE J. Solid State Circuits, August, 2024

2022

A Flexible 0.73-15.5 GHz Single LC VCO Clock Generator in 12 nm CMOS.

Haojie Xu, Bao Luo, Gaofeng Jin, Fei Feng, Huanan Guo, Xiang Gao

IEEE Trans. Circuits Syst. II Express Briefs, 2022

2021

A calibration-free multi-phase sampling Type-II PLL.

Haojie Xu, Gaofeng Jin, Jianan Wu, Huanan Guo, Xun Luo, Xiang Gao

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

2020

A Calibration-Free Low Spur Multi-Phase Sampling PLL.

Gaofeng Jin, Bao Luo, Xiang Gao

Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020