Gaurav Verma

Orcid: 0000-0001-7350-0813

Affiliations:
  • Jaypee Institute of Information Technology, Noida, India


According to our database1, Gaurav Verma authored at least 13 papers between 2017 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2025
FPGA Implementation and Performance Analysis of Parallel Prefix Structures for Modular Adders Design.
Circuits Syst. Signal Process., February, 2025

2022
Low Cost Smart Ground System for Rainwater Harvesting for Indian Houses using IoT Technology.
Wirel. Pers. Commun., 2022

Performance Analysis of CGOH, Parrallelized and Pipelined ALU for Low Power FPGA Implementations in IOT Framework.
Wirel. Pers. Commun., 2022

Power Estimation and Validation of Embedded Multiplier Based on ANN and Regression Technique.
J. Circuits Syst. Comput., 2022

Electricity Theft Detection and Localization in Smart Grids for Industry 4.0.
Intell. Autom. Soft Comput., 2022

2021
Vehicle Pollution Monitoring, Control and Challan System Using MQ2 Sensor Based on Internet of Things.
Wirel. Pers. Commun., 2021

2019
Heuristic and Statistical Power Estimation Model for FPGA Based Wireless Systems.
Wirel. Pers. Commun., 2019

More Precise FPGA Power Estimation and Validation Tool (FPEV_Tool) for Low Power Applications.
Wirel. Pers. Commun., 2019

3D Multilayer Mesh NoC Communication and FPGA Synthesis.
Wirel. Pers. Commun., 2019

2018
Real-Time Implementation of Parallel Architecture Based Noise Minimization from Speech Signals on FPGA.
Wirel. Pers. Commun., 2018

2017
Analysis of Low Power Consumption Techniques on FPGA for Wireless Devices.
Wirel. Pers. Commun., 2017

Low Power Synthesis and Validation of an Embedded Multiplier for FPGA Based Wireless Communication Systems.
Wirel. Pers. Commun., 2017

FM Receiver Design Using Programmable PLL.
Wirel. Pers. Commun., 2017


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