Gholamreza Ardeshir

Orcid: 0000-0002-2154-1514

According to our database1, Gholamreza Ardeshir authored at least 28 papers between 2001 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Variable bit allocation method based on meta-heuristic algorithms for facial image compression.
Multim. Syst., December, 2023

Compression of face images using meta-heuristic algorithms based on curvelet transform with variable bit allocation.
Multim. Syst., December, 2023

A new method of facial image compression based on meta-heuristic algorithms with variable bit budget allocation.
Signal Image Video Process., November, 2023

A general jitter analysis of DLL considering the jitter accumulation effect of loop capacitor.
Microprocess. Microsystems, 2023

Design and analysis of a novel fast adder using logical effort method.
IET Comput. Digit. Tech., 2023

2021
A low power and jitter delay cell with pulse width modulation for wide range delay lock loops.
Microelectron. J., 2021

Analysis and design of a low jitter delay-locked loop using lock state detector.
Int. J. Circuit Theory Appl., 2021

Novel quantum-dot cellular automata implementation of flip-flop and phase-frequency detector based on nand-nor-inverter gates.
Int. J. Circuit Theory Appl., 2021

2020
A Low-Power and High-Frequency Phase Frequency Detector for a 3.33-GHz Delay Locked Loop.
Circuits Syst. Signal Process., 2020

2019
An efficient voltage to delay conversion method for DCVSL cells and its application in high speed all-digital time-based quantization.
Int. J. Circuit Theory Appl., 2019

A mathematical method to realize complex poles in a high-order passive switched-capacitor filter.
Int. J. Circuit Theory Appl., 2019

2018
Low-power and wide-band delay-locked loop with switching delay line.
Int. J. Circuit Theory Appl., 2018

2017
Analysis of Millimeter-Wave LC Oscillators Based on Two-Port Network Theory.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

2015
A new fast-lock, low-jitter, and all-digital frequency synthesizer for DVB-T receivers.
Int. J. Circuit Theory Appl., 2015

2014
Jitter of Delay-Locked Loops Due to PFD.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Digital delay locked loop-based frequency synthesiser for Digital Video Broadcasting-Terrestrial receivers.
IET Circuits Devices Syst., 2014

Design of Novel Testable and Diagnosable Phase-Frequency Detector.
Circuits Syst. Signal Process., 2014

A novel algebraic method for kernel-based object tracking.
Comput. Electr. Eng., 2014

Facial Expression Recognition Using Facial Graph.
Proceedings of the Face and Facial Expression Recognition from Real World Videos, 2014

2013
Analysis of DLL Jitter due to Voltage-Controlled Delay Line.
Circuits Syst. Signal Process., 2013

2011
A novel architecture for low voltage-low power DLL-based frequency multipliers.
IEICE Electron. Express, 2011

2007
A New Signal Type Classifier for Fading Environments.
J. Comput. Inf. Technol., 2007

2004
Decision Tree Simplification For Classifier Ensembles.
Int. J. Pattern Recognit. Artif. Intell., 2004

2003
Spectral Coefficients and Classifier Correlation.
Proceedings of the Multiple Classifier Systems, 4th International Workshop, 2003

2002
Decision tree simplification for classifier ensembles.
PhD thesis, 2002

Boosted Tree Ensembles for Solving Multiclass Problems.
Proceedings of the Multiple Classifier Systems, Third International Workshop, 2002

Tree Pruning for Output Coded Ensembles.
Proceedings of the 16th International Conference on Pattern Recognition, 2002

2001
An Empirical Comparison of Pruning Methods for Ensemble Classifiers.
Proceedings of the Advances in Intelligent Data Analysis, 4th International Conference, 2001


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