Govind Prasad

According to our database, Govind Prasad authored at least 10 papers between 2016 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

NIR-DST: Noise-Immune Radiation Hardened Dual-Modal Domino-Schmitt Architecture.

Het Patel, Lakshya Singhal, Sai Ankit Sahoo, Anmol Aggarwal, Govind Prasad

Proceedings of the 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems, 2026

2025

DTQ-16T: Double Node Upset Tolerant Quadruple SRAM for Space Applications.

Pramod Kumar Bharti, Govind Prasad, Mukku Pavan Kumar, Joycee Mekie

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024

SEDONUT: A Single Event Double Node Upset Tolerant SRAM for Terrestrial Applications.

Govind Prasad, Bipin Chandra Mandi, Maifuz Ali

ACM Trans. Design Autom. Electr. Syst., May, 2024

Design of an SRAM-bitcell with enhanced self-recoverability from soft errors for space and critical terrestrial applications.

Govind Prasad, Bipin Chandra Mandi, Maifuz Ali

Integr., 2024

2022

Energy-efficient radiation hardened SRAM cell for low voltage terrestrial applications.

Govind Prasad, Bipin Chandra Mandi, Maifuz Ali

Microelectron. J., 2022

Novel low-power and stable memory cell design using hybrid CMOS and MTJ.

Govind Prasad, Deeksha Sahu, Bipin Chandra Mandi, Maifuz Ali

Int. J. Circuit Theory Appl., 2022

2020

Power optimized SRAM cell with high radiation hardened for aerospace applications.

Govind Prasad, Bipin Chandra Mandi, Maifuz Ali

Microelectron. J., 2020

Design and statistical analysis of low power and high speed 10T static random access memory cell.

Govind Prasad, Neha Kumari, Bipin Chandra Mandi, Maifuz Ali

Int. J. Circuit Theory Appl., 2020

2019

Design and Analysis of 10T-Boosted Radiation Hardened SRAM Cell for Aerospace Applications.

Govind Prasad, Bipin Chandra Mandi, Maifuz Ali

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

2016

Design and analysis of phase locked loop in 90nm CMOS.

Gande Bhargav, Govind Prasad, Srikar Datta Canchi, Badam Chanikya

Proceedings of the Thirteenth International Conference on Wireless and Optical Communications Networks, 2016