Grzegorz Bazydlo

Orcid: 0000-0003-3103-4767

Affiliations:
  • University of Zielona Góra, Poland


According to our database1, Grzegorz Bazydlo authored at least 15 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Supervisory Control of Cyber-Physical Systems Subject to Actuator Jamming Attacks.
Proceedings of the IEEE International Conference on Networking, Sensing and Control, 2023

Preliminary Verification of Liveness in a Control Part of Cyber-Physical Systems Modeled by a Petri Net.
Proceedings of the Technological Innovation for Connected Cyber Physical Spaces, 2023

Hippo-CPS: A Tool for Verification and Analysis of Petri Net-Based Cyber-Physical Systems.
Proceedings of the Application and Theory of Petri Nets and Concurrency, 2023

2022
Trusted and Secure Blockchain-Based Durable Medium Electronic Service.
Cryptogr., 2022

Analysis of Control Part of Cyber-Physical Systems Specified by Interpreted Petri Nets.
Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics, 2022

Hippo-CPS: Verification of Boundedness, Safeness and Liveness of Petri Net-Based Cyber-Physical Systems.
Proceedings of the Technological Innovation for Digitalization and Virtualization, 2022

2021
Analysis of safeness in a Petri net-based specification of the control part of cyber-physical systems.
Int. J. Appl. Math. Comput. Sci., 2021

2020
Dual-model approach for safety-critical embedded systems.
Microprocess. Microsystems, 2020

2019
Low-Cost FPGA Hardware Implementation of Matrix Converter Switch Control.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

SVM algorithm oriented for implementation in a low-cost Xilinx FPGA.
Integr., 2019

Petri Net-Based Specification of Cyber-Physical Systems Oriented to Control Direct Matrix Converters With Space Vector Modulation.
IEEE Access, 2019

Analysis and Design Automation of Cyber-Physical System with Hippo and IOPT-Tools.
Proceedings of the IECON 2019, 2019

2017
Dynamic Partial Reconfiguration of Concurrent Control Systems Implemented in FPGA Devices.
IEEE Trans. Ind. Informatics, 2017

2014
Translation UML diagrams into Verilog.
Proceedings of the 7th International Conference on Human System Interactions, 2014

2013
From UML State Machine Diagram into FPGA Implementation.
Proceedings of the 12th IFAC Conference on Programmable Devices and Embedded Systems, 2013


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