Guddeti Jayakrishna

According to our database1, Guddeti Jayakrishna authored at least 9 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

2023
Method to Generate Bus Stress Pattern Using iBUS(Infineon Bus Under Stress) framework.
Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023

2022
Enabling Automotive Electrification on Heterogeneous Automotive Microcontroller using Virtual System Modelling.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

2018
A Methodology to Validate the On-Chip Buses of a Microcontroller.
Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

2017
Automated test generation for post silicon microcontroller validation.
Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017

A method/approach leading to controlled randomization in validation of an IP.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

2016
FPGA based validation technique for Advanced Driver Assistance System.
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

Automotive micro-controller interface protocol silicon validation using PWM based protocol emulator.
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

Automotive microcontroller interface protocol validation in post-silicon using on-the-fly error injector.
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

Automation of FPGA based pin muxing for automotive SoC validation.
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016


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