Guoqiang Bai

Affiliations:
  • Tsinghua University, Institute of Microelectronics, Beijing, China


According to our database1, Guoqiang Bai authored at least 39 papers between 2006 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
Attention-based Efficient Lightweight Model for Accurate Real-Time Face Verification on Embedded Device.
Proceedings of the 6th IEEE International Conference on Computer and Communication Systems, 2021

2019
Hardware Implementation of Convolutional Neural Network for Face Feature Extraction.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
Differential Power Attack on SM4 Block Cipher.
Proceedings of the 17th IEEE International Conference On Trust, 2018

2017
Efficient hardware implementation of ITUbee for lightweight application.
Proceedings of the 12th International Conference for Internet Technology and Secured Transactions, 2017

2016
A Family of Scalable Polynomial Multiplier Architectures for Ring-LWE Based Cryptosystems.
IACR Cryptol. ePrint Arch., 2016

Efficient Hardware Implementation of Roadrunner for Lightweight Application.
Proceedings of the 2016 IEEE Trustcom/BigDataSE/ISPA, 2016

A Very Compact Masked S-Box for High-Performance Implementation of SM4 Based on Composite Field.
Proceedings of the Security and Privacy in Communication Networks, 2016

Towards efficient polynomial multiplication for lattice-based cryptography.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Efficient polynomial multiplier architecture for Ring-LWE based public key cryptosystems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

High-Speed Polynomial Multiplier Architecture for Ring-LWE Based Public Key Cryptosystems.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Detecting first-order leakages against the tower field masking scheme.
Proceedings of the International Conference on Computer, 2016

Specific hardware implementation for cofactorization in GNFS.
Proceedings of the International Conference on Computer, 2016

2015
Towards Efficient Implementation of Lattice-Based Public-Key Encryption on Modern CPUs.
Proceedings of the 2015 IEEE TrustCom/BigDataSE/ISPA, 2015

A Family of Scalable Polynomial Multiplier Architectures for Lattice-Based Cryptography.
Proceedings of the 2015 IEEE TrustCom/BigDataSE/ISPA, 2015

An efficient method for integer factorization.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Ultra High-Performance ASIC Implementation of SM2 with SPA Resistance.
Proceedings of the Information and Communications Security - 17th International Conference, 2015

Strategy of Relations Collection in Factoring RSA Modulus.
Proceedings of the Information and Communications Security - 17th International Conference, 2015

Towards efficient discrete Gaussian sampling for lattice-based cryptography.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Efficient Modular Reduction Algorithm Without Correction Phase.
Proceedings of the Frontiers in Algorithmics - 9th International Workshop, 2015

Improving Second-Order DPA Attacks with New Modeled Power Leakages.
Proceedings of the 11th International Conference on Computational Intelligence and Security, 2015

2014
Ultra High-Speed SM2 ASIC Implementation.
Proceedings of the 13th IEEE International Conference on Trust, 2014

Attacks on Physically-Embedded Data Encryption for Embedded Devices.
Proceedings of the 13th IEEE International Conference on Trust, 2014

On trojan side channel design and identification.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A Novel Relative Frequency Based Ring Oscillator Physical Unclonable Function.
Proceedings of the 17th IEEE International Conference on Computational Science and Engineering, 2014

Exploring the speed limit of SM2.
Proceedings of the IEEE 3rd International Conference on Cloud Computing and Intelligence Systems, 2014

A Novel Technique for Ring Oscillator Based PUFs to Enroll Stable Challenge Response Pairs.
Proceedings of the 14th IEEE International Conference on Computer and Information Technology, 2014

A randomized window-scanning RSA scheme resistant to power analysis.
Proceedings of the 2014 IEEE/ACIS 13th International Conference on Computer and Information Science, 2014

2011
Integration of information security chips based on System-in-Package.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Design and implementation of pipelined TMVP multiplier using block recombination.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
A Gbps IPSec SSL Security Processor Design and Implementation in an FPGA Prototyping Platform.
J. Signal Process. Syst., 2010

2009
A New Method to Reduce the Side-Channel Leakage Caused by Unbalanced Capacitances of Differential Interconnections in Dual-Rail Logic Styles.
Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009

A DPA-Resistant Digit-Parallel Modular Multiplier over GF (2m).
Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009

2008
A dual-field elliptic curve cryptographic processor based on a systolic arithmetic unit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Zodiac: System architecture implementation for a high-performance Network Security Processor.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007
A High-Performance Elliptic Curve Cryptographic Processor for General Curves Over GF(p) Based on a Systolic Arithmetic Unit.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

A New Systolic Architecture for Modular Division.
IEEE Trans. Computers, 2007

A Novel Unified Control Architecture for a High-Performance Network Security Accelerator.
Proceedings of the 2007 International Conference on Security & Management, 2007

2006
Convergence Study of Discrete Neural Networks with Delay.
Proceedings of the Neural Information Processing, 13th International Conference, 2006

Stability Conditions for Discrete Hopfield Neural Networks with Delay.
Proceedings of the Intelligent Computing, 2006


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