Gwon Kim
Orcid: 0000-0002-5488-9314Timeline
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Bibliography
2025
Study of 3-D Line Edge Roughness (LER) in Vertical Channel Array Transistor for DRAM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2025
Device Design Guidelines to Boost Up AC Performance of CFET (Complementary Field-Effect-Transistor)-Based Inverter.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2025