Gyung-Su Byun

Orcid: 0000-0002-6505-8663

According to our database¹, Gyung-Su Byun authored at least 20 papers between 2014 and 2025.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2025

Automated Internal Defect Identification and Localization Based on a Near-Field SAR Millimeter-Wave Imaging System.

[BibT_eX]

[DOI]

IEEE Access, 2025

2024

A High-Speed HBM Receiver Design for High-Performance Computing Systems.

[BibT_eX]

[DOI]

Thinh Nguyen-Viet

Gyung-Su Byun

Proceedings of the 21st International SoC Design Conference, 2024

Analysis and Design of CRC-based SENT Interface for Future Automotive Applications.

[BibT_eX]

[DOI]

Proceedings of the 21st International SoC Design Conference, 2024

2021

The Comparison Features of ECG Signal with Different Sampling Frequencies and Filter Methods for Real-Time Measurement.

[BibT_eX]

[DOI]

Ngoc Thang Bui

Gyung-Su Byun

Symmetry, 2021

A High-speed Wireless Data Transfer for Non - Destructive Testing.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

2018

Three-Dimensional Pipeline ADC Utilizing TSV/ Design Optimization and Memristor Ratioed Logic.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

A Wide-Range Low-Power PLL-Based PI Multiphase Generator Using an Adaptive Frequency Tracking Technique.

[BibT_eX]

[DOI]

Majid Jalalifar

Gyung-Su Byun

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Design of a Pre-Distortion Power Amplifier for Ku-Band/5G Applications.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Conference on Electro/Information Technology, 2018

A 3D flash ADC structure for high-speed communication applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE 8th Annual Computing and Communication Workshop and Conference, 2018

2017

An Energy-Efficient Mobile Memory I/O Interface Using Simultaneous Bidirectional Multilevel Dual-Band Signaling.

[BibT_eX]

[DOI]

Majid Jalalifar

Gyung-Su Byun

IEEE Trans. Circuits Syst. II Express Briefs, 2017

Automatic Design and Yield Enhancement of Data Converters.

[BibT_eX]

[DOI]

Nahid Mirzaie

Hossein Shamsi

Gyung-Su Byun

J. Circuits Syst. Comput., 2017

Yield-aware sizing of pipeline ADC using a multiple-objective evolutionary algorithm.

[BibT_eX]

[DOI]

Nahid Mirzaie

Hossein Shamsi

Gyung-Su Byun

Int. J. Circuit Theory Appl., 2017

A performance-aware I/O interface for 3D stacked memory systems.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE Annual Ubiquitous Computing, 2017

Low-power and high-performance 2.4 GHz RF transmitter for biomedical application.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE Annual Ubiquitous Computing, 2017

A low-power and performance-efficient SAR ADC design.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2017

High-performance RF-interconnect for 3D stacked memory.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2017

2016

A 14.4Gb/s/pin 230fJ/b/pin/mm multi-level RF-interconnect for global network-on-chip communication.

[BibT_eX]

[DOI]

Majid Jalalifar

Gyung-Su Byun

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

A Low-Power 4-PAM Transceiver Using a Dual-Sampling Technique for Heterogeneous Latency-Sensitive Network-on-Chip.

[BibT_eX]

[DOI]

Gyung-Su Byun

Mir Mohammad Navidi

IEEE Trans. Circuits Syst. II Express Briefs, 2015

2014

Comparative analysis of clock distribution networks for TSV-based 3D IC designs.

[BibT_eX]

[DOI]

Mir Mohammad Navidi

Gyung-Su Byun

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

An energy-efficient mobile PAM memory interface for future 3D stacked mobile DRAMs.

[BibT_eX]

[DOI]

Majid Jalalifar

Gyung-Su Byun

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Gyung-Su Byun

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