H. V. Ravish Aradhya

According to our database, H. V. Ravish Aradhya authored at least 3 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of six.

2025

A Novel Algorithm for Aspect Ratio Estimation in SRAM Design to Achieve High SNM, High Speed, and Low Leakage Power.

Sanket M. Mantrashetti, Arunkumar P. Chavan, Prakash Pawar, H. V. Ravish Aradhya, Omkar S. Powar

IEEE Access, 2025

2024

A Novel TriNet Architecture for Enhanced Analog IC Design Automation.

Arunkumar P. Chavan, Shrish Shrinath Vaidya, Sanket M. Mantrashetti, Abhishek Gurunath Dastikopp, Kishan S. Murthy, H. V. Ravish Aradhya, Prakash Pawar

IEEE Trans. Very Large Scale Integr. Syst., November, 2024

Hardware in loop network simulators - An insight overview.

G. Sushanth, H. V. Ravish Aradhya

Int. J. Model. Simul. Sci. Comput., February, 2024