Hajime Nagano

According to our database, Hajime Nagano authored at least 1 paper in 2004.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of six.

2004

Low power logic circuit and SRAM cell applications with silicon on depletion layer CMOS (SODEL CMOS) technology.

Satoshi Inaba, Hajime Nagano, Kiyotaka Miyano, Ichiro Mizushima, Yasunori Okayama, Takahiro Nakauchi, Kazunari Ishimaru, Hidemi Ishiuchi

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004