Helena Krupnova

According to our database, Helena Krupnova authored at least 16 papers between 1997 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2026

Physical Synthesis/layout Issues Specific to FPGA-based Emulation.

Helena Krupnova

Proceedings of the 2026 International Symposium on Physical Design, 2026

2004

Deploying Hardware Platforms for SoC Validation: An Industrial Case Study.

Anne Bigot, Fabrice Charpentier, Helena Krupnova, Isabelle Sans

Proceedings of the Field Programmable Logic and Application, 2004

Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and Experience.

Helena Krupnova

Proceedings of the 2004 Design, 2004

2002

How Fast Is Rapid FPGA-based Prototyping: Lessons and Challenges from the Digital TV Design Prototyping Project.

Helena Krupnova, Veronique Meurou, Christophe Barnichon, Carlos Serra, Farid Morsi

Proceedings of the Field-Programmable Logic and Applications, 2002

2000

FPGA Technology Snapshot: Current Devices and Design Tools.

Helena Krupnova, Gabriele Saucier

Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000

FPGA-Based Emulation: Industrial and Custom Prototyping Solutions.

Helena Krupnova, Gabriele Saucier

Proceedings of the Field-Programmable Logic and Applications, 2000

1999

FPGA Partitioning for Rapid Prototyping: A 1 Million Gate Design Case Study.

Helena Krupnova, Christian Rabedaoro, Gabriele Saucier

Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999

Hierarchical Interactive Approach to Partition Large Designs into FPGAs.

Helena Krupnova, Gabriele Saucier

Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

Partitioning Large Designs by Filling PFGA Devices with Hierarchy Blocks.

Helena Krupnova, Gabriele Saucier

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs.

Helena Krupnova, Gabriele Saucier

Proceedings of the 1999 Design, 1999

1998

Real Time Prototyping Method and a Case Study.

Helena Krupnova, Dinh Duc Anh Vu, Gabriele Saucier, Michel Boubal

Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998

A Knowledge-Based System for Prototyping on FPFAs.

Helena Krupnova, Vu DucAnh Dinh, Gabriele Saucier

Proceedings of the Field-Programmable Logic and Applications, 1998

Timing Driven Floorplanning on Programmable Hierarchical Targets.

S. A. Senouci, Aadil Amoura, Helena Krupnova, Gabriele Saucier

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Block and IP Wrapping for Efficient Design on FPGAs (Abstract).

Helena Krupnova, B. Behnam, Gabriele Saucier

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

1997

Synthesis and Floorplanning for Large Hierarchical FPGAs.

Helena Krupnova, Christian Rabedaoro, Gabriele Saucier

Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, 1997

A Hierarchy-Driven FPGA Partitioning Method.

Helena Krupnova, Ali Abbara, Gabriele Saucier

Proceedings of the 34st Conference on Design Automation, 1997