Henrik Valter

According to our database¹, Henrik Valter authored at least 2 papers between 2022 and 2024.

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2024

Higher-order Hardware: Implementation and Evaluation of the Cephalopode Graph Reduction Processor.

[DOI]

Proceedings of the 22nd ACM-IEEE International Symposium on Formal Methods and Models for System Design, 2024

2022

Energy-Efficiency Evaluation of OpenMP Loop Transformations and Runtime Constructs.

[DOI]

CoRR, 2022