Howard M. Heys
Orcid: 0000-0003-4506-3673
According to our database1,
Howard M. Heys
authored at least 53 papers
between 1994 and 2022.
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Bibliography
2022
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2020
A Tutorial on the Implementation of Block Ciphers: Software and Hardware Applications.
IACR Cryptol. ePrint Arch., 2020
Key Dependency of Differentials: Experiments in the Differential Cryptanalysis of Block Ciphers Using Small S-boxes.
IACR Cryptol. ePrint Arch., 2020
2019
Integr., 2019
Using deep learning to combine static and dynamic power analyses of cryptographic circuits.
Int. J. Circuit Theory Appl., 2019
2018
Template Attacks of a Masked S-Box Circuit: A Comparison Between Static and Dynamic Power Analyses.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
Distributed Time-Memory Tradeoff Attacks on Ciphers - (with Application to Stream Ciphers and Counter Mode).
Proceedings of the Information Security and Privacy - 23rd Australasian Conference, 2018
2017
Template attacks based on static power analysis of block ciphers in 45-nm CMOS environment.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
2016
Secur. Commun. Networks, 2016
2015
Application of Simple Power Analysis to Stream Ciphers Constructed Using Feedback Shift Registers.
Comput. J., 2015
Proceedings of the IEEE 28th Canadian Conference on Electrical and Computer Engineering, 2015
Proceedings of the IEEE 28th Canadian Conference on Electrical and Computer Engineering, 2015
2014
Performance Characterization of AES Datapath Architectures in 90-nm Standard Cell CMOS Technology.
J. Signal Process. Syst., 2014
Performance Characterization of Pipelined S-Box Implementations for the Advanced Encryption Standard.
J. Circuits Syst. Comput., 2014
IET Inf. Secur., 2014
2013
FPGA Implementation and Energy Cost Analysis of Two Light-Weight Involutional Block Ciphers Targeted to Wireless Sensor Networks.
Mob. Networks Appl., 2013
Analytic modeling of interconnect capacitance in submicron and nanometer technologies.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, 2013
A pipelined implementation of the grØstl hash algorithm and the advanced encryption standard.
Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, 2013
Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, 2013
2012
Secur. Commun. Networks, 2012
Applicability of simple power analysis to stream ciphers constructed using multiple LFSRs.
Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012
Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012
2011
Pipelined Statistical Cipher Feedback: A New Mode for High-Speed Self-Synchronizing Stream Encryption.
IEEE Trans. Computers, 2011
Proceedings of the 6th International ICST Conference on Communications and Networking in China, 2011
FPGA implementation of two involutional block ciphers targeted to wireless sensor networks.
Proceedings of the 6th International ICST Conference on Communications and Networking in China, 2011
2010
Proceedings of IEEE International Conference on Communications, 2010
2009
Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009
2008
IACR Cryptol. ePrint Arch., 2008
Compact ASIC implementation of the ICEBERG block cipher with concurrent error detection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
2007
Design and implementation of a scalable switch architecture for efficient high-speed data multicasting.
Int. J. Commun. Syst., 2007
An analytical approach to the performance evaluation of the balanced gamma switch under multicast traffic.
Int. J. Commun. Syst., 2007
2006
Proceedings of IEEE International Conference on Communications, 2006
Architecture and Performance Analysis of the Multicast Balanced Gamma Switch for Broadband Communications1.
Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006
2005
A simple power analysis attack against the key schedule of the Camellia block cipher.
Inf. Process. Lett., 2005
IACR Cryptol. ePrint Arch., 2005
2003
IEEE Trans. Computers, 2003
Proceedings of the Topics in Cryptology, 2003
2002
Proceedings of the Information Security and Cryptology, 2002
Proceedings of the 11th International Conference on Computer Communications and Networks, 2002
2001
Proceedings of the Proceedings IEEE INFOCOM 2001, 2001
1998
1997
Resistance of a CAST-Like Encryption Algorithm to Linear and Differential Cryptanalysis.
Des. Codes Cryptogr., 1997
1996
Substitution-Permutation Networks Resistant to Differential and Linear Cryptanalysis.
J. Cryptol., 1996
Cryptologia, 1996
1995
IEEE Trans. Computers, 1995
1994
The Design of Substitution-Permutation Networks Resistant to Differential and Linear Cryptanalysis.
Proceedings of the CCS '94, 1994