Lihong Zhang

According to our database1, Lihong Zhang authored at least 74 papers between 2002 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
EA-Based LDE-Aware Fast Analog Layout Retargeting With Device Abstraction.
IEEE Trans. VLSI Syst., 2019

Explicit Iteration and Unique Positive Solution for a Caputo-Hadamard Fractional Turbulent Flow Model.
IEEE Access, 2019

Graph-Grammar-Based Analog Circuit Topology Synthesis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Electromigration- and Parasitic-Aware ILP-Based Analog Router.
IEEE Trans. VLSI Syst., 2018

Analog Layout Retargeting With Process-Variation-Aware Hybrid OPC.
IEEE Trans. VLSI Syst., 2018

PV-Aware Analog Sizing for Robust Analog Layout Retargeting with Optical Proximity Correction.
ACM Trans. Design Autom. Electr. Syst., 2018

Density-Uniformity-Aware Analog Layout Retargeting.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

The Accurate Location Estimation of Sensor Node Using Received Signal Strength Measurements in Large-Scale Farmland.
J. Sensors, 2018

Nonlocal Hadamard fractional boundary value problem with Hadamard integral and discrete boundary conditions on a half-line.
J. Computational Applied Mathematics, 2018

Efficient parasitic-aware hybrid sizing methodology for analog and RF integrated circuits.
Integration, 2018

Cerebral activation effects of acupuncture at Yanglinquan(GB34) point acquired using resting-state fMRI.
Comp. Med. Imag. and Graph., 2018

Parasitic-aware gm/ID-based many-objective analog/RF circuit sizing.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Fast Performance Evaluation for Analog Circuit Synthesis Frameworks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Electromigration and Parasitic-Aware ILP Router for Analog and RF Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Layout-dependent effects aware gm/iD-based many-objective sizing optimization for analog integrated circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
The Propagation Characteristics of Radio Frequency Signals for Wireless Sensor Networks in Large-Scale Farmland.
Wireless Personal Communications, 2017

A Fast Hierarchical Adaptive Analog Routing Algorithm Based on Integer Linear Programming.
ACM Trans. Design Autom. Electr. Syst., 2017

Process-Variation-Aware Rule-Based Optical Proximity Correction for Analog Layout Migration.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Automated topology synthesis of analog and RF integrated circuits: A survey.
Integration, 2017

Analog layout density uniformity improvement using interconnect widening and dummy fill insertion.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Analog layout retargeting with process-variation-aware rule-based OPC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Parasitic-aware GP-based many-objective sizing methodology for analog and RF integrated circuits.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Lithography-Aware Analog Layout Retargeting.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Portable Wind Energy Harvesters for Low-Power Applications: A Survey.
Sensors, 2016

Message-locked proof of ownership and retrievability with remote repairing in cloud.
Security and Communication Networks, 2016

Intermediate Frequency Digital Receiver Based on Multi-FPGA System.
J. Electrical and Computer Engineering, 2016

Efficient ILP-based variant-grid analog router.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Advanced nanometer technology analog layout retargeting for lithography friendly design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
New Analytic Model of Coupling and Substrate Capacitance in Nanometer Technologies.
IEEE Trans. VLSI Syst., 2015

How Does the Internet Affect the Financial Market? An Equilibrium Model of Internet-Facilitated Feedback Trading.
MIS Quarterly, 2015

Explicit iterations and extremal solutions for fractional differential equations with nonlinear integral boundary conditions.
Applied Mathematics and Computation, 2015

Lithography-friendly analog layout migration.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Neutral fractional integro-differential equation with nonlinear term depending on lower order derivative.
J. Computational Applied Mathematics, 2014

A cross-nation comparative study of mobile learning.
IJMC, 2014

The existence of an extremal solution to a nonlinear system with the right-handed Riemann-Liouville fractional derivative.
Appl. Math. Lett., 2014

2013
Nonlinear fractional integro-differential equations on unbounded domains in a Banach space.
J. Computational Applied Mathematics, 2013

Existence results for a coupled system of nonlinear neutral fractional differential equations.
Appl. Math. Lett., 2013

Analytic modeling of interconnect capacitance in submicron and nanometer technologies.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Fast parasitic-aware synthesis methodology for high-performance analog circuits.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Analog layout retargeting using geometric programming.
ACM Trans. Design Autom. Electr. Syst., 2011

Boundary value problem for first order impulsive functional integro-differential equations.
J. Computational Applied Mathematics, 2011

Directly performance-constrained template-based layout retargeting and optimization for analog integrated circuits.
Integration, 2011

Some existence results for impulsive nonlinear fractional differential equations with mixed boundary conditions.
Computers & Mathematics with Applications, 2011

Improving Parallel FDTD Method Performance Using SSE Instructions.
Proceedings of the Fourth International Symposium on Parallel Architectures, 2011

Internet-Facilitated Feedback Trading.
Proceedings of the 44th Hawaii International International Conference on Systems Science (HICSS-44 2011), 2011

Multilevel fuzzy comprehensive evaluation of corporate quality culture - based on the entropy power method.
Proceedings of the Eighth International Conference on Fuzzy Systems and Knowledge Discovery, 2011

2010
Extremal solutions for the first order impulsive functional differential equations with upper and lower solutions in reversed order.
J. Computational Applied Mathematics, 2010

Symmetry-aware placement algorithm using transitive closure graph representation for analog integrated circuits.
I. J. Circuit Theory and Applications, 2010

Symmetry-aware analog layout placement design handling substrate-sharing constraints.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Performance-constrained template-driven retargeting for analog and RF layouts.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

A performance-constrained template-based layout retargeting algorithm for analog integrated circuits.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Symmetry-aware TCG-based placement design under complex multi-group constraints for analog circuit layouts.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
A routing-table-based adaptive and minimal routing scheme on network-on-chip architectures.
Computers & Electrical Engineering, 2009

Research on Remote Monitoring of Large-Scale Oil Tanks Based on Web.
Proceedings of the CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31, 2009

MOSFET model assessment for submicron and nanometer bulk-driven applications.
Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009

Performance-constrained parasitic-aware retargeting and optimization of analog layouts.
Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009

Analog placement design with constraints of multiple symmetry groups.
Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009

Artificial neural network application in analog layout placement design.
Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009

A Research on the Automatic Discovery Technology of Network Topology.
Proceedings of the 2nd International Conference on BioMedical Engineering and Informatics, 2009

2008
VLSI Circuit Layout.
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Symmetry-aware placement with transitive closure graphs for analog layout design.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2006
An automated design tool for analog layouts.
IEEE Trans. VLSI Syst., 2006

Placement Algorithm in Analog-Layout Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Ruin problems for a discrete time risk model with random interest rate.
Math. Meth. of OR, 2006

CCC Speaker Recognition Evaluation 2006: Overview, Methods, Data, Results and Perspective.
Proceedings of the Chinese Spoken Language Processing, 5th International Symposium, 2006

A Speech Recognition System Based on a Hybrid HMM/SVM Architecture.
Proceedings of the First International Conference on Innovative Computing, Information and Control (ICICIC 2006), 30 August, 2006

Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005
A hybrid evolutionary analogue module placement algorithm for integrated circuit layout designs.
I. J. Circuit Theory and Applications, 2005

Macro-cell placement for analog physical designs using a hybrid genetic algorithm with simulated annealing.
Integrated Computer-Aided Engineering, 2005

2004
A placement algorithm for implementation of analog LSI/VLSI systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A novel analog layout synthesis tool.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Layout synthesis of analog integrated circuits.
PhD thesis, 2003

2002
A genetic approach to analog module placement with simulated annealing.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002


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