J. Chithambara Moorthii

Orcid: 0009-0008-5124-9582

According to our database1, J. Chithambara Moorthii authored at least 6 papers between 2023 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
SIMMAC: SRAM IMC-Based Multibit Multiplication With Analog Carry Computation.
IEEE Embed. Syst. Lett., February, 2026

2025
Investigation of Security Vulnerabilities in NVM-Based Persistent TinyML Hardware.
IEEE Embed. Syst. Lett., June, 2025

DNA-CIM: DNA Sequence Analysis Using RRAM-Based Compute In-Memory Accelerator.
Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

Investigation of EM Fault Injection on Emerging Lightweight Neural Network Hardware.
Proceedings of the Applied Cryptography and Network Security Workshops, 2025

2024
VPU-CIM: A 130nm, 33.98 TOPS/W RRAM based Compute-In-Memory Vector Co-Processor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
NVSystolic: Heterogeneous Simulation Framework for Emerging Memories with Systolic Array.
Proceedings of the 19th International Conference on Synthesis, 2023


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