J. Ramesh

According to our database, J. Ramesh authored at least 4 papers between 2021 and 2025.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2025

Investigation of PNN Inverter-Based Low PDP 12T GNRFET Full Adder for VLSI Signal Processing Applications.

K. R. Radhakrishnan, J. Ramesh, M. Elangovan

J. Circuits Syst. Comput., February, 2025

2023

Correction to: An Efficient VLSI Architecture for Fast Motion Estimation Exploiting Zero Motion Prejudgment Technique and a New Quadrant Depended on Search Algorithm in HEVC.

C. Arunkumar Madhuvappan, J. Ramesh

Wirel. Pers. Commun., 2023

An Efficient VLSI Architecture for Fast Motion Estimation Exploiting Zero Motion Prejudgment Technique and a New Quadrant Depended on Search Algorithm in HEVC.

C. Arunkumar Madhuvappan, J. Ramesh

Wirel. Pers. Commun., 2023

2021

Channel estimation using spatial partitioning with coalitional game theory (SPCGT) in wireless communication.

S. Dhanasekaran, J. Ramesh

Wirel. Networks, 2021