J. Soares Augusto

Orcid: 0000-0002-5869-7950

According to our database1, J. Soares Augusto authored at least 9 papers between 1994 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

2014
A Multimodal Low-cost Platform for Acquisition of Electrophysiological Signals Interfacing with Portable Devices.
Proceedings of the PhyCS 2014, 2014

2011
Efficient time domain analogue fault simulation targeting nonlinear circuits.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2008
A Tool for Single-Fault Diagnosis in Linear Analog Circuits with Tolerance Using the T-Vector Approach.
VLSI Design, 2008

2003
A Modular Reconfigurable Architecture for Efficient Fault Simulation in Digital Circuits.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2000
Analog fault diagnosis in nonlinear DC circuits with an evolutionary algorithm.
Proceedings of the 2000 Congress on Evolutionary Computation, 2000

1999
FASTNR: an Efficient Fault Simulator for Linear and Nonlinear DC Circuits.
Proceedings of the VLSI: Systems on a Chip, 1999

1998
Circuit equations for fast fault simulation and diagnosis of linear circuits.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1995
Fully automatic DC fault dictionary construction and test nodes selection for analogue fault diagnosis.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
New Algorithms in Piecewise Linear Resistive Simulation.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994


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