Jagadish Dasarahalli Narasimaiah

According to our database, Jagadish Dasarahalli Narasimaiah authored at least 12 papers between 2014 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

Glomerulus Detection Using Segmentation Neural Networks.

Surender Singh Samant, Arun Chauhan, Jagadish D. N., Vijay Singh

J. Digit. Imaging, August, 2023

2022

Conditional Variational Autoencoder Networks for Autonomous Vehicle Path Prediction.

D. N. Jagadish, Arun Chauhan, Lakshman Mahto

Neural Process. Lett., 2022

2021

Autonomous Vehicle Path Prediction Using Conditional Variational Autoencoder Networks.

Jagadish D. N., Arun Chauhan, Lakshman Mahto

Proceedings of the Advances in Knowledge Discovery and Data Mining, 2021

Multimodality Data Fusion for COVID-19 Diagnosis.

Arun Chauhan, Jagadish D. N., Lakshman Mahto

Proceedings of the 2021 IEEE International Conference on Big Data (Big Data), 2021

2020

Density Based Clustering Methods for Road Traffic Estimation.

Jagadish D. N., Lakshman Mahto, Arun Chauhan

Proceedings of the 2020 IEEE Region 10 Conference, 2020

Detection of Reckless Driving using Deep Learning.

Arun Chauhan, Shobhan Kumar, Lakshman Mahto, Jagadish D. N.

Proceedings of the 19th IEEE International Conference on Machine Learning and Applications, 2020

Deep Learning and Density Based Clustering Methods for Road Traffic Prediction.

D. N. Jagadish, Lakshman Mahto, Arun Chauhan

Proceedings of the Computer Vision and Image Processing - 5th International Conference, 2020

2018

11.39 fJ/conversion-step 780 kS/s 8 bit switched capacitor-based area and energy-efficient successive approximation register ADC in 90 nm complementary metal-oxide-semiconductor.

Jagadish Dasarahalli Narasimaiah, Laxminidhi Tonse, Mujoor Sankaranarayana Bhat

IET Circuits Devices Syst., 2018

14.5 fJ/conversion-step 9-bit 100-kS/s non-binary weighted dual capacitor array based area and energy efficient SAR ADC in 90 nm CMOS.

Jagadish Dasarahalli Narasimaiah, Mujoor Shankaranarayana Bhat

IET Circuits Devices Syst., 2018

2015

Low Energy and Area Efficient Nonbinary Capacitor Array Based Successive Approximation Register Analog-to-Digital Converter.

D. N. Jagadish, M. S. Bhat

J. Low Power Electron., 2015

2014

A Low Voltage Inverter Based Differential Amplifier for Low Power Switched Capacitor Applications.

D. N. Jagadish, M. S. Bhat

Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

Low Energy and Area Efficient Nonbinary Capacitor Array Based SAR ADC.

D. N. Jagadish, M. S. Bhat

Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014