James Coole

According to our database, James Coole authored at least 11 papers between 2008 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

A Recurrently Generated Overlay Architecture for Rapid FPGA Application Development.

David Wilson, Greg Stitt, James Coole

Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

2017

Developing Dynamic Profiling and Debugging Support in OpenCL for FPGAs.

Anshuman Verma, Huiyang Zhou, Skip Booth, Robbie King, James Coole, Andy Keep, John Marshall, Wu-chun Feng

Proceedings of the 54th Annual Design Automation Conference, 2017

2015

Adjustable-Cost Overlays for Runtime Compilation.

James Coole, Greg Stitt

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014

Fast, Flexible High-Level Synthesis from OpenCL using Reconfiguration Contexts.

James Coole, Greg Stitt

IEEE Micro, 2014

2012

BPR: fast FPGA placement and routing using macroblocks.

James Coole, Greg Stitt

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011

Intermediate Fabrics: Virtual Architectures for Near-Instant FPGA Compilation.

Greg Stitt, James Coole

IEEE Embed. Syst. Lett., 2011

An End-to-End Tool Flow for FPGA-Accelerated Scientific Computing.

Greg Stitt, Alan D. George, Herman Lam, Melissa C. Smith, Vikas Aggarwal, Gongyu Wang, Casey Reardon, Brian Holland, Seth Koehler, James Coole

IEEE Des. Test Comput., 2011

2010

Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures.

James Coole, Greg Stitt

Int. J. Reconfigurable Comput., 2010

Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing.

James Coole, Greg Stitt

Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009

A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body Simulation.

James Coole, John Robert Wernsing, Greg Stitt

Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

2008

Traversal caches: a first step towards FPGA acceleration of pointer-based data structures.

Greg Stitt, Gaurav Chaudhari, James Coole

Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008