Jangseok Yu

Orcid: 0009-0003-9719-5456

According to our database¹, Jangseok Yu authored at least 3 papers between 2025 and 2026.

Collaborative distances:

Timeline

Book In proceedings Article PhD thesis Dataset Other

2026

Speeding-Up Successive Read Operations of STT-MRAM via Read Path Alternation for Delay Symmetry.

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2026

A FeFET-based Approximate DCIM Integrating Multiplication and OR Addition In-Bitcell.

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025

HR<sup>2</sup>: A PVT Aware Hierarchical RL Based Sizing Framework for Robust Analog Circuit Design.

[DOI]

Proceedings of the 7th ACM/IEEE Symposium on Machine Learning for CAD, 2025