According to our database1, Jean-Paul Bodeveix
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An Event-B framework for the validation of Event-B refinement plugins.
Automatic Refinement for Event-B through Annotated Patterns.
Proceedings of the 25th Euromicro International Conference on Parallel, 2017
A refinement-based compiler development for synchronous languages.
Proceedings of the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2017
Towards a verified compiler prototype for the synchronous language SIGNAL.
Frontiers Comput. Sci., 2016
An Event-B Development Process for the Distributed BIP Framework.
Proceedings of the Formal Methods and Software Engineering, 2016
Towards a verified transformation from AADL to the formal component-based language FIACRE.
Sci. Comput. Program., 2015
Real-Time Model Checking Support for AADL.
From AADL to Timed Abstract State Machines: A verified model transformation.
Journal of Systems and Software, 2014
A verified transformation: from polychronous programs to a variant of clocked guarded actions.
Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems, 2014
Multi-Core Code Generation from Polychronous Programs with Time-Predictable Properties.
Proceedings of the First International Workshop on Architecture Centric Virtual Integration co-located with the 17th International Conference on Model Driven Engineering Languages and Systems, 2014
A comparative study of two formal semantics of the SIGNAL language.
Frontiers Comput. Sci., 2013
Event Algebra for Transition Systems Composition - Application to Timed Automata.
Proceedings of the 2013 20th International Symposium on Temporal Representation and Reasoning, 2013
Extending UPPAAL for the Modeling and Verification of Dynamic Real-Time Systems.
Proceedings of the Fundamentals of Software Engineering - 5th International Conference, 2013
A Mechanized Semantic Framework for Real-Time Systems.
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2013
An Automatic Technique for Checking the Simulation of Timed Systems.
Proceedings of the Automated Technology for Verification and Analysis, 2013
Compositional Refinement for Real-Time Systems with Priorities.
Proceedings of the 19th International Symposium on Temporal Representation and Reasoning, 2012
Revising and Extending the Uppaal Communication Mechanism.
Proceedings of the Software Composition - 11th International Conference, 2012
Event B Development of a Synchronous AADL Scheduler.
Electr. Notes Theor. Comput. Sci., 2011
Design of a BPEL Verification Tool.
Proceedings of the Web Services and Formal Methods - 8th International Workshop, 2011
Two Formal Semantics of a Subset of the AADL.
Proceedings of the 16th IEEE International Conference on Engineering of Complex Computer Systems, 2011
Verification of Timed BPEL 2.0 Models.
Proceedings of the Enterprise, Business-Process and Information Systems Modeling, 2011
An Alternative Definition for Timed Automata Composition.
Proceedings of the Automated Technology for Verification and Analysis, 2011
Supporting the Design of Safety Critical Systems Using AADL.
Proceedings of the 15th IEEE International Conference on Engineering of Complex Computer Systems, 2010
Polychronous Interpretation of Synoptic, a Domain Specific Modeling Language for Embedded Flight-Software
Proceedings of the Proceedings FM-09 Workshop on Formal Methods for Aerospace, 2009
Towards Safe Design of Synchronous Bus Protocols in Event-B.
Proceedings of the Formal Methods: Foundations and Applications, 2009
A Comparative Study of FIACRE and TASM to Define AADL Real Time Concepts.
Proceedings of the 14th IEEE International Conference on Engineering of Complex Computer Systems, 2009
Modeling AADL Data Communication with BIP.
Proceedings of the Reliable Software Technologies, 2009
Formal Verification of AADL Specifications in the Topcased Environment.
Proceedings of the Reliable Software Technologies, 2009
Spécification et vérification d'un ordonnanceur en B via les automates temporisés.
Modes in Asynchronous Systems.
Proceedings of the 13th International Conference on Engineering of Complex Computer Systems (ICECCS 2008), March 31 2008, 2008
Automatic Verification of Bossa Scheduler Properties.
Electr. Notes Theor. Comput. Sci., 2007
A mapping from AADL to Java-RTSJ.
Proceedings of the 5th International Workshop on Java Technologies for Real-time and Embedded Systems, 2007
The AADL behaviour annex - experiments and roadmap.
Proceedings of the 12th International Conference on Engineering of Complex Computer Systems (ICECCS 2007), 2007
Security policy compliance with violation management.
Proceedings of the 2007 ACM workshop on Formal methods in security engineering, 2007
Verification of a scheduler in B through a timed automata specification.
Proceedings of the 2006 ACM Symposium on Applied Computing (SAC), 2006
A State/Event Temporal Deontic Logic.
Proceedings of the Deontic Logic and Artificial Normative Systems, 2006
Towards formalising AADL in Proof Assistants.
Electr. Notes Theor. Comput. Sci., 2005
Formal Methods Meet Domain Specific Languages.
Proceedings of the Integrated Formal Methods, 5th International Conference, 2005
TransM: A Structured Document Transformation Model.
Proceedings of the Information Systems Technology and its Applications, 2004
Towards the verification of real-time systems in avionics: the Cotre approach.
Electr. Notes Theor. Comput. Sci., 2003
Vérification de modèles UML fondée sur OCL.
Proceedings of the Actes du XXIème Congrès INFORSID, Nancy, France, 24-27 mai, 2003, 2003
Reduction and Quantifier Elimination Techniques for Program Validation.
Formal Methods in System Design, 2002
Type Synthesis in B and the Translation of B to PVS.
Proceedings of the ZB 2002: Formal Specification and Development in Z and B, 2002
Abstract machine construction through operational semantics refinements.
Future Generation Comp. Syst., 2000
FMona: A Tool for Expressing Validation Techniques over Infinite State Systems.
Proceedings of the Tools and Algorithms for Construction and Analysis of Systems, 2000
Experimenting Acceleration Methods for the Validation of Infinite State Systems.
Proceedings of the 2000 ICDCS Workshops, April 10, 2000, Taipei, Taiwan, ROC, 2000
A Concurrent Object-Based Model and its Use for Coordinating Java Components.
Proceedings of the TOOLS 1999: 30th International Conference on Technology of Object-Oriented Languages and Systems, Delivering Quality Software, 1999
Types versus classes.
On the Automatic Validation of Parameterized Unity Programs.
IPPS/SPDP Workshops, 1998
Towards the Automatic Verification of Atomic Memory Protocols.
Parallel Processing Letters, 1997
On the Refinement of symmetric memory protocols.
Proceedings of the Higher Order Logic Theorem Proving and Its Applications, 1995
Towards a HOL Theory and Memory.
Proceedings of the Higher Order Logic Theorem Proving and Its Applications, 1994
A Parallel Prolog Execution Model Theoretical Approach and Experimental Results.
Proceedings of the Seventh International Parallel Processing Symposium, 1993