Jeong-Sup Lee
According to our database1,
Jeong-Sup Lee
authored at least 7 papers
between 2008 and 2017.
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Bibliography
2017
A 103.125-Gb/s Reverse Gearbox IC in 40-nm CMOS for Supporting Legacy 10- and 40-GbE Links.
IEEE J. Solid State Circuits, 2017
2016
A Power-and-Area Efficient 10 × 10 Gb/s Bootstrap Transceiver in 40 nm CMOS for Referenceless and Lane-Independent Operation.
IEEE J. Solid State Circuits, 2016
2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE J. Solid State Circuits, 2015
A 100-GbE reverse gearbox IC in 40nm CMOS for supporting legacy 10- and 40-GbE standards.
Proceedings of the Symposium on VLSI Circuits, 2015
A power-and-area efficient 10 × 10 Gb/s bootstrap transceiver in 40 nm CMOS for reference-less and lane-independent operation.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2008
Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008