In-Cheol Park

According to our database1, In-Cheol Park authored at least 175 papers between 1990 and 2020.

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Bibliography

2020
A 120-mW 0.16-ms-Latency Connectivity-Scalable Multiuser Detector for Interleave Division Multiple Access.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Low-Latency Multi-Touch Detector Based on Concurrent Processing of Redesigned Overlap Split and Connected Component Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Retrain-Less Weight Quantization for Multiplier-Less Convolutional Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Large-Small Sorting for Successive Cancellation List Decoding of Polar Codes.
IEEE Access, 2020

2019
Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Parallel IDMA Architecture Based on Interleaving with Replicated Subpatterns.
Proceedings of the 2019 IEEE International Conference on Communications, 2019

2018
A Fast Successive Cancellation List Decoder for Polar Codes With an Early Stopping Criterion.
IEEE Trans. Signal Process., 2018

Fast Low-Complexity Triple-Error-Correcting BCH Decoding Architecture.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Energy-Efficient Convolution Architecture Based on Rescheduled Dataflow.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Memory-Efficient IDMA Architecture Based on On-the-Fly Despreading.
IEEE J. Solid State Circuits, 2018

DSIP: A Scalable Inference Accelerator for Convolutional Neural Networks.
IEEE J. Solid State Circuits, 2018

Efficient Implementation of Multiple Interleavers in IDMA for 5G.
Proceedings of the International SoC Design Conference, 2018

Interference Cancellation Architecture for Pipelined Parallel MIMO Detectors.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

A 2.4pJ/bit, 6.37Gb/s SPC-enhanced BC-BCH decoder in 65nm CMOS for NAND flash storage systems.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Low-Power LDPC-CC Decoding Architecture Based on the Integration of Memory Banks.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

High-Performance Low-Area Video Up-Scaling Architecture for 4-K UHD Video.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Improved Sorting Architecture for K-Best MIMO Detection.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Low-Latency Low-Cost Architecture for Square and Cube Roots.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Improved Hard-Reliability Based Majority-Logic Decoding for Non-Binary LDPC Codes.
IEEE Commun. Lett., 2017

Multi-Bit Flipping Decoding of LDPC Codes for NAND Storage Systems.
IEEE Commun. Lett., 2017

Improved Successive-Cancellation Decoding of Polar Codes Based on Recursive Syndrome Decomposition.
IEEE Commun. Lett., 2017

An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storages.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Low-Power Parallel Chien Search Architecture Using a Two-Step Approach.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Area-Efficient Approach for Generating Quantized Gaussian Noise.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Energy-Scalable 4KB LDPC Decoding Architecture for NAND-Flash-Based Storage Systems.
IEICE Trans. Electron., 2016

Efficient Pruning for Successive-Cancellation Decoding of Polar Codes.
IEEE Commun. Lett., 2016

Low-complexity symbol detection for massive MIMO uplink based on Jacobi method.
Proceedings of the 27th IEEE Annual International Symposium on Personal, 2016

2015
Partially Parallel Encoder Architecture for Long Polar Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Reverse Rate Matching for Low-Power LTE-Advanced Turbo Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Low-Complexity Tree Architecture for Finding the First Two Minima.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Efficient Parallel Architecture for Linear Feedback Shift Registers.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Unidirectional ring ethernet for low-complexity in-vehicle control network.
Proceedings of the IEEE International Conference on Industrial Technology, 2015

Narrow-range frequency estimation based on comprehensive optimization of DFT and interpolation.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015

2014
High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A search-less DEC BCH decoder for low-complexity fault-tolerant systems.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

7.3 Gb/s universal BCH encoder and decoder for SSD controllers.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Area-Efficient Multimode Encoding Architecture for Long BCH Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Low-Complexity Parallel QPP Interleaver Based on Permutation Patterns.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory.
IEEE J. Solid State Circuits, 2013

Area-Efficient QC-LDPC Decoder Architecture Based on Stride Scheduling and Memory Bank Division.
IEICE Trans. Commun., 2013

Efficient Tree-Traversal Strategy for Soft-Output MIMO Detection Based on Candidate-Set Reorganization.
IEEE Commun. Lett., 2013

Memory-Optimized Hybrid Decoding Method for Multi-Rate Turbo Codes.
Proceedings of the 77th IEEE Vehicular Technology Conference, 2013

Adaptive Metric Calculation for Improving Detection Capability of MIMO Detectors.
Proceedings of the 77th IEEE Vehicular Technology Conference, 2013

A 3Gb/s 2.08mm<sup>2</sup> 100b error-correcting BCH decoder in 0.13µm CMOS process.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Low-Complexity Tone Reservation for PAPR Reduction in OFDM Communication Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2012

FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Immediate Exchange of Extrinsic Information for High-Throughput Turbo Decoding.
IEEE Commun. Lett., 2012

SNR-Adaptive Input Quantization for Turbo Decoding.
Proceedings of the 75th IEEE Vehicular Technology Conference, 2012

6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Low-latency area-efficient decoding architecture for shortened reed-solomon codes.
Proceedings of the International SoC Design Conference, 2012

Small-area parallel syndrome calculation for strong BCH decoding.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

2011
Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Efficient Pruning for Infinity-Norm Sphere Decoding Based on Schnorr-Euchner Enumeration.
IEICE Trans. Commun., 2011

Division-less high-radix interleaved modular multiplication using a scaled modulus.
Proceedings of the International SoC Design Conference, 2011

Statistical modeling of capacitor mismatch effects for successive approximation register ADCs.
Proceedings of the International SoC Design Conference, 2011

QC-LDPC Decoding Architecture based on Stride Scheduling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Design of a Scalable and Programmable Sound Synthesizer.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Optimization of Arithmetic Coding for JPEG2000.
IEEE Trans. Circuits Syst. Video Technol., 2010

Spur-Free MASH Delta-Sigma Modulation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Small-Area and Low-Energy K -Best MIMO Detector Using Relaxed Tree Expansion and Early Forwarding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

High-Throughput and Area-Efficient MIMO Symbol Detection Based on Modified Dijkstra's Search.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Multiplier-less and Table-less Linear Approximation for Square-Related Functions.
IEICE Trans. Inf. Syst., 2010

Small-area and low-energy <i>K</i>-best MIMO detector using relaxed tree expansion and early forwarding.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Low-complexity tone reservation method for PAPR reduction of OFDM systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Capacitor array structure and switching control scheme to reduce capacitor mismatch effects for SAR analog-to-digital converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Dual-rail decoding of low-density parity-check codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Low-complex BPSK demodulation using absolute comparison.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

A 2.6Gb/s 1.56mm<sup>2</sup> near-optimal MIMO detector in 0.18µm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Pipelined Discrete Wavelet Transform Architecture Scanning Dual Lines.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Bit-Level Extrinsic Information Exchange Method for Double-Binary Turbo Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A novel trace-pipelined binary arithmetic coder architecture for JPEG2000.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Novel Pipelined DWT Architecture for Dual-line Scan.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Fast Frequency Acquisition Phase Frequency Detectors with Prediction-based edge Blocking.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Scalable and Programmable Sound Synthesizer.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Memory-less bit-plane coder architecture for JPEG2000 with concurrent column-stripe coding.
Proceedings of the International Conference on Image Processing, 2009

Architecture design of a high-performance dual-symbol binary arithmetic coder for JPEG2000.
Proceedings of the International Conference on Image Processing, 2009

Multiplier-less and table-less linear approximation for square and square-root.
Proceedings of the 27th International Conference on Computer Design, 2009

Implementation of a High-Throughput and Area-Efficient MIMO Detector Based on Modified Dijkstra's Search.
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009

A unified parallel radix-4 turbo decoder for mobile WiMAX and 3GPP-LTE.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Low-Power and High-Accurate Synchronization for IEEE 802.16d Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Double-Binary Circular Turbo Decoding Based on Border Metric Encoding.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Time-Domain Joint Estimation of Fine Symbol Timing Offset and Integer Carrier Frequency Offset.
Proceedings of the 67th IEEE Vehicular Technology Conference, 2008

Prediction-based real-time CABAC decoder for high definition H.264/AVC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Fast frequency acquisition all-digital PLL using PVT calibration.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Digital filter synthesis considering multiple adder graphs for a coefficient.
Proceedings of the 26th International Conference on Computer Design, 2008

Area and power efficient design of coarse time synchronizer and frequency offset estimator for fixed WiMAX systems.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Duo-binary circular turbo decoder based on border metric encoding for WiMAX.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Balanced Binary-Tree Decomposition for Area-Efficient Pipelined FFT Processing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Pipelined Cartesian-to-Polar Coordinate Conversion Based on SRT Division.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Parallel Decoding of Context-Based Adaptive Binary Arithmetic Codes Based on Most Probable Symbol Prediction.
IEICE Trans. Inf. Syst., 2007

Long-Point FFT Processing Based on Twiddle Factor Table Reduction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Fast and Area-Efficient Sphere Decoding Using Look-Ahead Search.
Proceedings of the 65th IEEE Vehicular Technology Conference, 2007

Two-Step Aprroach for Coarse Time Synchronization and Frequency Offset Estimation for IEEE 802.16D Systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Tiled Interleaving for Multi-Level 2-D Discrete Wavelet Transform.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Energy-Efficient Double-Binary Tail-Biting Turbo Decoder Based on Border Metric Encoding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

High Speed Sphere Decoding Based on Vertically Incremental Computation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Twiddle factor transformation for pipelined FFT processing.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
Low-power log-MAP decoding based on reduced metric memory access.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Loosely coupled memory-based decoding architecture for low density parity check codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Low-Power Hybrid Turbo Decoding Based on Reverse Calculation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Combined image signal processing for CMOS image sensors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High speed decoding of context-based adaptive binary arithmetic codes using most probable symbol prediction.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Hybrid ΣΔ modulators with adaptive calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

SAT-based unbounded symbolic model checking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Performance enhancement of embedded software based on new register allocation technique.
Microprocess. Microsystems, 2005

A Low-Complexity Stopping Criterion for Iterative Turbo Decoding.
IEICE Trans. Commun., 2005

Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Low-power log-MAP turbo decoding based on reduced metric memory access.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A scalable SIMD digital signal processor for high-quality multifunctional printer systems.
Proceedings of the Color Imaging X: Processing, Hardcopy, and Applications, San Jose, 2005

2004
Quadrature direct digital frequency synthesis using fine-grain angle rotation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A fast Reed-Solomon Product-Code decoder without redundant computations.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Memory-based low density parity check code decoder architecture using loosely coupled two data-flows.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
Address code generation for DSP instruction-set architectures.
ACM Trans. Design Autom. Electr. Syst., 2003

High performance memory mode control for HDTV decoders.
IEEE Trans. Consumer Electron., 2003

Timed compiled-code functional simulation of embedded software for performance analysis of SOC design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Processor-based turbo interleaver for multiple third-generation wireless standards.
IEEE Commun. Lett., 2003

A hybrid delta-sigma modulator with adaptive calibration.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

History-based memory mode prediction for improving memory performance.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Area-efficient memory-based architecture for FFT processing.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 24-bit floating-point audio DSP controller supporting fast exponentiation.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Pairing and ordering to reduce hardware complexity in cascade form filter design.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 5-GHz self-calibrated I/Q clock generator using a quadrature LC-VCO.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Low-power hybrid structure of digital matched filters for direct sequence spread spectrum systems.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

2002
Digital filter synthesis based on an algorithm to generate all minimal signed digit representations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Interface synthesis between software chip model and target board.
J. Syst. Archit., 2002

Area-efficient digital baseband module for Bluetooth wireless communications.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Low cost floating-point unit design for audio applications.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A high-speed and low-latency Reed-Solomon decoder based on a dual-line structure.
Proceedings of the IEEE International Conference on Acoustics, 2002

Timed compiled-code simulation of embedded software for performance analysis of SOC design.
Proceedings of the 39th Design Automation Conference, 2002

2001
High-performance and low-power memory-interface architecture for video processing applications.
IEEE Trans. Circuits Syst. Video Technol., 2001

A fixed-point MPEG audio processor operating at low frequency.
IEEE Trans. Consumer Electron., 2001

A low-power variable length decoder based on successive decoding of shoft codewords.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Global variable localization and transformation for hardware synthesis from high-level programming language description.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Digital Filter Synthesis Based on Minimal Signed Digit Representation.
Proceedings of the 38th Design Automation Conference, 2001

Low-power high-level synthesis using latches.
Proceedings of ASP-DAC 2001, 2001

2000
MetaCore: an application-specific programmable DSP development system.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Optimal down-conversion in compressed DCT domain with minimal operations.
Proceedings of the Visual Communications and Image Processing 2000, 2000

Array address translation for SDRAM-based video processing applications.
Proceedings of the Visual Communications and Image Processing 2000, 2000

Pyramid Texture Compression and Decompression Using Interpolative Vector Quantization.
Proceedings of the 2000 International Conference on Image Processing, 2000

Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphics.
Proceedings of ASP-DAC 2000, 2000

1999
Synthesis of Application Specific Instructions for Embedded DSP Software.
IEEE Trans. Computers, 1999

Path-based branch prediction using signature analysis.
Microprocess. Microsystems, 1999

A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders.
Proceedings of the IEEE International Conference On Computer Design, 1999

Customization of a CISC Processor Core for Low-Power Applications.
Proceedings of the IEEE International Conference On Computer Design, 1999

Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software.
Proceedings of the 36th Conference on Design Automation, 1999

Verification of a Microprocessor Using Real World Applications.
Proceedings of the 36th Conference on Design Automation, 1999

A New Single-Clock Flip-Clop for Half-Swing Clocking.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
Synthesis of application specific instructions for embedded DSP software.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Multiple Behavior Module Synthesis Based on Selective Groupings.
Proceedings of the 1998 Design, 1998


Virtual Chip: Making Functional Models Work on Real Target Systems.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Design Verification of Complex Microprocessors.
J. Circuits Syst. Comput., 1997

A C-Based RTL Design Verification Methodology for Complex Microprocessor.
Proceedings of the 34st Conference on Design Automation, 1997

Verification methodology of compatible microprocessors.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

Single cycle access cache for the misaligned data and instruction prefetch.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

Multi-project chip activities in Korea-IDEC perspective.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

HK386: an x86-compatible 32-bit CISC microprocessor.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1994
Two Complementary Approaches for Microcode Bit Optimization.
IEEE Trans. Computers, 1994

1993
FAMOS: an efficient scheduling algorithm for high-level synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1991
Fast and Near Optimal Scheduling in Automatic Data Path Aynthesis.
Proceedings of the 28th Design Automation Conference, 1991

1990
An O(<i>n</i><sup>3</sup>log<i>n</i>)-Heuristic for Microcode Bit Optimization.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990


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