Jian Wu

Orcid: 0000-0003-2308-9207

Affiliations:

Taiwan Semiconductor Manufacturing Company, Shanghai, China
Zhejiang University, Department of Information Science and Electronic Engineering, Hangzhou, China (2010 - 2013)

According to our database¹, Jian Wu authored at least 5 papers between 2011 and 2016.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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Book

In proceedings

Article

PhD thesis

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Bibliography

2016

300-V class power n-channel LDMOS transistor implemented in 0.18-μm silicon-on-insulator (SOI) technology.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2016

2012

A novel power-clamp assisted complementary MOSFET for robust ESD protection.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2012

A novel gate-suppression technique for ESD protection.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2012

Investigation of ESD protection strategy in high voltage Bipolar-CMOS-DMOS process.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2012

2011

Substrate-engineered GGNMOS for low trigger voltage ESD in 65 nm CMOS process.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2011

Jian Wu

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On csauthors.net:

Bibliography

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