Jianhui Yue

Orcid: 0000-0002-1876-6931

According to our database1, Jianhui Yue authored at least 31 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A hybrid memory architecture supporting fine-grained data migration.
Frontiers Comput. Sci., April, 2024

FlashGNN: An In-SSD Accelerator for GNN Training.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023
RACE: An Efficient Redundancy-aware Accelerator for Dynamic Graph Neural Network.
ACM Trans. Archit. Code Optim., December, 2023

Object Fingerprint Cache for Heterogeneous Memory System.
IEEE Trans. Computers, September, 2023

Cocktail: Mixing Data With Different Characteristics to Reduce Read Reclaims for nand Flash Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

2022
FlashWalker: An In-Storage Accelerator for Graph Random Walks.
Proceedings of the 2022 IEEE International Parallel and Distributed Processing Symposium, 2022

Accelerate Hardware Logging for Efficient Crash Consistency in Persistent Memory.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Trade-off Between Hit Rate and Hit Latency for Optimizing DRAM Cache.
IEEE Trans. Emerg. Top. Comput., 2021

Efficient NVM Crash Consistency by Mitigating Resource Contention.
Proceedings of the IEEE International Conference on Networking, Architecture and Storage, 2021

Efficient Hardware Redo Logging for Secure Persistent Memory.
Proceedings of the 2021 IEEE 23rd Int Conf on High Performance Computing & Communications; 7th Int Conf on Data Science & Systems; 19th Int Conf on Smart City; 7th Int Conf on Dependability in Sensor, 2021

Efficient Hardware-assisted Out-place Update for Persistent Memory.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Improving the Performance of NVM Crash Consistency under Multicore.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Efficient Hardware-Assisted Crash Consistency in Encrypted Persistent Memory.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2017
Enhancing the Malloc System with Pollution Awareness for Better Cache Performance.
IEEE Trans. Parallel Distributed Syst., 2017

2016
Reducing Read Latency in MLC PCM.
Proceedings of the IEEE International Conference on Networking, 2016

2015
NightWatch: Integrating Lightweight and Transparent Cache Pollution Control into Dynamic Memory Allocation Systems.
Proceedings of the 2015 USENIX Annual Technical Conference, 2015

SFMapReduce: An optimized MapReduce framework for Small Files.
Proceedings of the 10th IEEE International Conference on Networking, 2015

2014
Performance-energy adaptation of parallel programs in pervasive computing.
J. Supercomput., 2014

2013
Accelerating write by exploiting PCM asymmetries.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

Exploiting subarrays inside a bank to improve phase change memory performance.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Making Write Less Blocking for Read Accesses in Phase Change Memory.
Proceedings of the 20th IEEE International Symposium on Modeling, 2012

Temporal characterization of SPEC CPU2006 workloads: Analysis and synthesis.
Proceedings of the 31st IEEE International Performance Computing and Communications Conference, 2012

2011
Energy Efficient Buffer Cache Replacement for Data Servers.
Proceedings of the Sixth International Conference on Networking, Architecture, and Storage, 2011

Hot Random Off-Loading: A Hybrid Storage System with Dynamic Data Migration.
Proceedings of the MASCOTS 2011, 2011

2010
Energy and thermal aware buffer cache replacement algorithm.
Proceedings of the IEEE 26th Symposium on Mass Storage Systems and Technologies, 2010

2008
An Energy-Oriented Evaluation of Buffer Cache Algorithms Using Parallel I/O Workloads.
IEEE Trans. Parallel Distributed Syst., 2008

An Energy-Efficient Buffer Cache Replacement.
Proceedings of the 16th International Symposium on Modeling, 2008

Impacts of Indirect Blocks on Buffer Cache Energy Efficiency.
Proceedings of the 2008 International Conference on Parallel Processing, 2008

2007
Evaluating memory energy efficiency in parallel I/O workloads.
Proceedings of the 2007 IEEE International Conference on Cluster Computing, 2007

2004
Global Backfilling Scheduling in Multiclusters.
Proceedings of the Applied Computing, Second Asian Applied Computing Conference, 2004

2003
HARTs: high availability cluster architecture with redundant TCP stacks.
Proceedings of the 22nd IEEE International Performance Computing and Communications Conference, 2003


  Loading...