Jingcheng Tao

According to our database, Jingcheng Tao authored at least 5 papers between 2018 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

A 2.3 GHz 2.8 mW Sampling ΔΣ PLL Achieving -110 dBc/Hz In-Band Phase Noise and 500 MHz FMCW Chirp.

Hanyang Su, Jingcheng Tao, Siegfred D. Balon, Chun-Huat Heng

IEEE J. Solid State Circuits, 2021

2020

ΔΣ Fractional-N PLL With Hybrid IIR Noise Filtering.

Jingcheng Tao, Chun-Huat Heng

IEEE Trans. Circuits Syst. II Express Briefs, 2020

2019

A 2.2-GHz 3.2-mW DTC-Free Sampling ΔΣ Fractional-N PLL With -110-dBc/Hz In-Band Phase Noise and -246-dB FoM and -83-dBc Reference Spur.

Jingcheng Tao, Chun-Huat Heng

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 2.2-GHz 3.2-mW DTC-free Sampling ΔΣ Fractional-N PLL with -110 dBc/Hz In-band phase noise and -246dB FoM and -83dBc Reference Spur.

Jingcheng Tao, Chun-Huat Heng

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018

A 1.6-GHz 3.3-mW 1.5-MHz Wide Bandwidth ΔΣ Fractional-N PLL with a Single Path FIR Phase Noise Filtering.

Jingcheng Tao, Chun-Huat Heng

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018