Jizhang Chen

According to our database, Jizhang Chen authored at least 4 papers between 2024 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

A 1500 V/ μ s slew rate, 300 MHz GBW operational amplifier in 0.18- μ m HV BCD process for CMOS system-level monolithic integration.

Jizhang Chen, Jueping Cai, Yuxin Zhang, Yixin Yin, Boming Tang

Microelectron. J., 2026

2025

A 285-nA Quiescent Current, 94.7% Peak Efficiency Buck Converter With AOT Control for IoT Application.

Yuxin Zhang, Jueping Cai, Jizhang Chen, Lifeng Jiang, Yixin Yin

IEEE Trans. Very Large Scale Integr. Syst., April, 2025

A novel 8T2R NVSRAM with synchronizing write and store function.

Bowen Su, Jueping Cai, Yuxin Zhang, Jizhang Chen, Yiding Wang

Microelectron. J., 2025

2024

A 0.91-μA-quiescent-current capacitor-less LDO with sub-threshold transient enhancement and bulk-driven feed-forward supply ripple cancellation.

Yuxin Zhang, Jueping Cai, Jizhang Chen, Lifeng Jiang

Microelectron. J., 2024