José A. Tierno

According to our database1, José A. Tierno authored at least 33 papers between 1994 and 2015.

Collaborative distances:
  • Dijkstra number2 of two.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2015
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2015

2014
Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A 28 GHz Hybrid PLL in 32 nm SOI CMOS.
IEEE J. Solid State Circuits, 2014

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Active Guardband Management in Power7+ to Save Energy and Maintain Reliability.
IEEE Micro, 2013

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing.
IEEE J. Solid State Circuits, 2013

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL.
IEEE J. Solid State Circuits, 2013

A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS.
IEEE J. Solid State Circuits, 2012

An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012


2011
Introducing the Adaptive Energy Management Features of the Power7 Chip.
IEEE Micro, 2011

Adaptive energy-management features of the IBM POWER7 chip.
IBM J. Res. Dev., 2011

Active management of timing guardband to save energy in POWER7.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Indirect phase noise sensing for self-healing voltage controlled oscillators.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz.
IEEE Trans. Very Large Scale Integr. Syst., 2010

2009
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI.
IEEE J. Solid State Circuits, 2008

A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

1998
Asynchronous Parallel Prefix Computation.
IEEE Trans. Computers, 1998

Asynchronous Circuits and Systems in Superconducting RSFQ Digital Technology.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998

1997
Asynchronous Transpose-Matrix Architectures.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996
The energy and entropy of VLSI computations.
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996

1994
A 100-MIPS GaAs Asynchronous Microprocessor.
IEEE Des. Test Comput., 1994

Low-energy asynchronous memory design.
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994


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