Jose Cisneros

According to our database, Jose Cisneros authored at least 5 papers between 2017 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

A 1024-Channel 10-Bit 36-$\mu$W/ch CMOS ROIC for Multiplexed GFET-Only Sensor Arrays in Brain Mapping.

Jose Cisneros-Fernández, Ramon Garcia-Cortadella, Xavi Illa, Javier Martínez-Aguilar, Jens Paetzold, Rainer Mohrlok, Marius Kurnoth, Christoph Jeschke, Lluís Terés, Jose A. Garrido, Anton Guimerà-Brunet, Francisco Serra-Graells

IEEE Trans. Biomed. Circuits Syst., 2021

2020

A 1024-Channel GFET 10-bit 5-kHz 36-μW Read-Out Integrated Circuit for Brain JLECoG.

Jose Cisneros-Fernández, Anton Guimerà-Brunet, Ramon Garcia-Cortadella, Nathan Schäfer, Jose A. Garrido, Lluís Terés, Francisco Serra-Graells

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019

Switch-Less Frequency-Domain Multiplexing of GFET Sensors and Low-Power CMOS Frontend for 1024-Channel μECoG.

Jose Cisneros-Fernández, Michele Dei, Lluís Terés, Francisco Serra-Graells

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

A Compact Switched-Capacitor Multi-Bit Quantizer for Low-Power High-Resolution Delta-Sigma ADCs.

Jose Cisneros-Fernández, Francisco Serra-Graells, Lluís Terés, Michele Dei

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

A Robust 96.6-dB-SNDR 50-kHz-Bandwidth Switched-Capacitor Delta-Sigma Modulator for IR Imagers in Space Instrumentation.

Michele Dei, Stepan Sutula, Jose Cisneros, Ernesto Pun, Richard Jan Engel Jansen, Lluís Terés, Francisco Serra-Graells

Sensors, 2017