Jose Luis Nunes

According to our database, Jose Luis Nunes authored at least 7 papers between 2011 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Improving FPGA resilience through Partial Dynamic Reconfiguration.

Jose Luis Nunes

CoRR, 2016

Using Failure Prediction to Improve FPGA Scrubbing.

Jose Luis Nunes, João Carlos Cunha, Mário Zenha Rela

Proceedings of the 2016 Seventh Latin-American Symposium on Dependable Computing, 2016

On the Effects of Cumulative SEUs in FPGA-Based Systems.

Jose Luis Nunes, João Carlos Cunha, Mário Zenha Rela

Proceedings of the 12th European Dependable Computing Conference, 2016

2015

FIRED - Fault Injector for Reconfigurable Embedded Devices.

Jose Luis Nunes, Tamas Pecserke, João Carlos Cunha, Mário Zenha Rela

Proceedings of the 21st IEEE Pacific Rim International Symposium on Dependable Computing, 2015

2013

Evaluating Xilinx SEU Controller Macro for fault injection.

Jose Luis Nunes, João Carlos Cunha, Raul Barbosa, Mário Zenha Rela

Proceedings of the 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2013

Improving the dependability of FPGA-based real-time embedded systems with partial dynamic reconfiguration.

Jose Luis Nunes

Proceedings of the 43rd Annual IEEE/IFIP Conference on Dependable Systems and Networks Workshop, 2013

2011

Using partial dynamic FPGA reconfiguration to support real-time dependability.

José Luís Nunes, João Carlos Cunha, Raul Barbosa, Mário Zenha Rela

Proceedings of the 13th European Workshop on Dependable Computing, 2011