José L. Núñez-Yáñez
Orcid: 0000-0002-5153-5481Affiliations:
- University of Linköping, Sweden
- University of Bristol, UK (former)
According to our database1,
José L. Núñez-Yáñez
authored at least 124 papers
between 2001 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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on orcid.org
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on bris.ac.uk
On csauthors.net:
Bibliography
2024
Optimisation and Evaluation of Breadth First Search with oneAPI/SYCL on Intel FPGAs: from Describing Algorithms to Describing Architectures.
Proceedings of the 12th International Workshop on OpenCL and SYCL, 2024
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024
2023
Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite.
Microprocess. Microsystems, April, 2023
CoRR, 2023
EnergyAnalyzer: Using Static WCET Analysis Techniques to Estimate the Energy Consumption of Embedded Applications.
Proceedings of the 21th International Workshop on Worst-Case Execution Time Analysis, 2023
Multiple Human Tracking and Fall Detection Real-Time System Using Millimeter-Wave Radar and Data Fusion.
Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023
2022
IEEE Micro, 2022
J. Syst. Archit., 2022
Robust and Accurate Fine-Grain Power Models for Embedded Systems With No On-Chip PMU.
IEEE Embed. Syst. Lett., 2022
Accurate Energy Modelling on the Cortex-M0 Processor for Profiling and Static Analysis.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
Evaluation of Early-exit Strategies in Low-cost FPGA-based Binarized Neural Networks.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2022
2021
Energy-efficient neural networks with near-threshold processors and hardware accelerators.
J. Syst. Archit., 2021
Sparse and dense matrix multiplication hardware for heterogeneous multi-precision neural networks.
Array, 2021
2020
J. Supercomput., 2020
A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Int. J. Embed. Syst., 2020
CoRR, 2020
Performance and Energy Trade-Offs for Parallel Applications on Heterogeneous Multi-Processing Systems.
CoRR, 2020
Remaining Useful Life Estimation Using Long Short-Term Memory Neural Networks and Deep Fusion.
IEEE Access, 2020
Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling.
Proceedings of the 11th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures / 9th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2020
Proceedings of the 11th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures / 9th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2020
2019
Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA.
J. Supercomput., 2019
J. Supercomput., 2019
Energy Proportional Neural Network Inference with Adaptive Voltage and Frequency Scaling.
IEEE Trans. Computers, 2019
J. Syst. Archit., 2019
Performance and Energy Efficiency Trade-Offs in Single-ISA Heterogeneous Multi-Processing for Parallel Applications.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019
Proceedings of the Machine Learning, Optimization, and Data Science, 2019
Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2019
2018
ACM Trans. Embed. Comput. Syst., 2018
Int. J. Reconfigurable Comput., 2018
Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems.
CoRR, 2018
Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Microprocess. Microsystems, 2017
Adaptive voltage scaling in a heterogeneous FPGA device with memory and logic in-situ detectors.
Microprocess. Microsystems, 2017
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Proceedings of the Parallel Computing is Everywhere, 2017
Proceedings of the Parallel Computing is Everywhere, 2017
A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Optimal compression of vibration data with lifting wavelet transform and context-based arithmetic coding.
Proceedings of the 25th European Signal Processing Conference, 2017
2016
IEEE Trans. Computers, 2016
EURASIP J. Embed. Syst., 2016
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Computing to the Limit with Heterogeneous CPU-FPGA Devices in a Video Fusion Application.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016
2015
IEEE Trans. Computers, 2015
Microprocess. Microsystems, 2015
Proceedings of the Parallel Computing: On the Road to Exascale, 2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015
2014
IEEE Trans. Circuits Syst. Video Technol., 2014
SIGARCH Comput. Archit. News, 2014
IET Comput. Digit. Tech., 2014
eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip.
IET Comput. Digit. Tech., 2014
Proceedings of the NCTA 2014 - Proceedings of the International Conference on Neural Computation Theory and Applications, part of IJCCI 2014, Rome, Italy, 22, 2014
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Proceedings of the FPGA World Conference 2014, 2014
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014
2013
IEEE Trans. Computers, 2013
Enabling accurate modeling of power and energy consumption in an ARM-based System-on-Chip.
Microprocess. Microsystems, 2013
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Proceedings of the IEEE International Conference on Image Processing, 2013
Proceedings of the 10th FPGAworld Conference, 2013
2012
Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding.
IEEE Trans. Very Large Scale Integr. Syst., 2012
ACM Trans. Reconfigurable Technol. Syst., 2012
IEEE Signal Process. Lett., 2012
Lossless video compression based on backward adaptive pixel-based fast motion estimation.
Signal Process. Image Commun., 2012
Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation.
IET Comput. Digit. Tech., 2012
Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles.
IET Comput. Digit. Tech., 2012
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012
Proceedings of the 20th European Signal Processing Conference, 2012
2011
IET Comput. Digit. Tech., 2011
2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
SystemC Architectural Transaction Level Modelling for Large NoCs.
Proceedings of the 2010 Forum on specification & Design Languages, 2010
2009
IEEE Signal Process. Lett., 2009
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
A toolset for the analysis and optimization of motion estimation algorithms and processors.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
Energy optimization in a Network-on-Chip with dynamically reconfigurable processing nodes.
Proceedings of the IEEE International Conference on Control Applications, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study.
Integr., 2008
Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems.
IET Comput. Digit. Tech., 2008
Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor.
Proceedings of the FPL 2008, 2008
A configurable and programmable motion estimation processor for the H.264 video codec.
Proceedings of the FPL 2008, 2008
Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
Proceedings of the Reconfigurable Computing: Architectures, 2008
Statistical Lossless Compression of Space Imagery and General Data in a Reconfigurable Architecture.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008
2007
Hardware architecture for lossless image compression based on context-based modeling and arithmetic coding.
Proceedings of the 2007 IEEE International SOC Conference, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the FPL 2007, 2007
2006
Hardware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec.
IEEE Trans. Consumer Electron., 2006
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006
2005
High-performance arithmetic coding VLSI macro for the H264 video compression standard.
IEEE Trans. Consumer Electron., 2005
IEEE Trans. Consumer Electron., 2005
A Configurable Statistical Lossless Compression Core Based on Variable Order Markov Modeling and Arithmetic Coding.
IEEE Trans. Computers, 2005
Applying data-parallel and scalar optimizations for the efficient implementation of the G.729A and G.723.1 speech coding standards.
Proceedings of the Signal and Image Processing (SIP 2005), 2005
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005
2003
IEEE Trans. Consumer Electron., 2003
Proceedings of the 2003 International Symposium on System-on-Chip, 2003
2001