José O. Cadenas

According to our database, José O. Cadenas authored at least 31 papers between 1999 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Non-uniform quantization with linear average-case computation time.

Oswaldo Cadenas, Graham M. Megson

CoRR, 2021

2019

Running Median Algorithm and Implementation for Integer Streaming Applications.

Oswaldo Cadenas, Graham M. Megson

IEEE Embed. Syst. Lett., 2019

2018

KurSL: Model of Anharmonic Coupled Oscillations Based on Kuramoto Coupling and Sturm-Liouville Problem.

Dawid Laszuk, José O. Cadenas, Slawomir J. Nasuto

Adv. Data Sci. Adapt. Anal., 2018

2016

On the Phase Coupling of Two Components Mixing in Empirical Mode Decomposition.

Dawid Laszuk, José O. Cadenas, Slawomir J. Nasuto

Adv. Data Sci. Adapt. Anal., 2016

2015

Virtualization for Cost-Effective Teaching of Assembly Language Programming.

José O. Cadenas, Robert Simon Sherratt, Des Howlett, Chris G. Guy, Karsten Øster Lundqvist

IEEE Trans. Educ., 2015

Median Filter Architecture by Accumulative Parallel Counters.

José O. Cadenas, Graham M. Megson, Robert Simon Sherratt

IEEE Trans. Circuits Syst. II Express Briefs, 2015

An Empirical Evaluation of Preconditioning Data for Accelerating Convex Hull Computations.

José O. Cadenas, Graham M. Megson

CoRR, 2015

Objective Empirical Mode Decomposition metric.

Dawid Laszuk, Oswaldo Cadenas, Slawomir J. Nasuto

Proceedings of the 38th International Conference on Telecommunications and Signal Processing, 2015

2014

Acceleration and visualization of Dynamic Network Optimization.

Yuanzhou Ye, Oswaldo Cadenas, Graham M. Megson

Proceedings of the International Conference on Computing, Networking and Communications, 2014

2013

C-slow retimed parallel histogram architectures for consumer imaging devices.

José O. Cadenas, Robert Simon Sherratt, Pablo Huerta, Wen-Chung Kao, Graham M. Megson

IEEE Trans. Consumer Electron., 2013

A Parallel Quantum Histogram Architecture.

Graham M. Megson, José O. Cadenas, Robert Simon Sherratt, Pablo Huerta, Wen-Chung Kao

IEEE Trans. Circuits Syst. II Express Briefs, 2013

A Rank-based Convex Hull method for Dense Data Sets

Graham M. Megson, José O. Cadenas

CoRR, 2013

Asynchronous distributed parallelization of mobile network optimization algorithms.

Yuanzhou Ye, Graham M. Megson, Oswaldo Cadenas

Proceedings of the 3rd International Conference on Wireless Communications, 2013

Distributed parallelization of greedy Mobile Network Optimization algorithms.

Yuanzhou Ye, Oswaldo Cadenas, Graham M. Megson

Proceedings of the 21st International Conference on Software, 2013

Parallel pipelined histogram architecture via C-slow retiming.

José O. Cadenas, R. Simon Sherratt, Pablo Huerta, Wen-Chung Kao, Graham M. Megson

Proceedings of the IEEE International Conference on Consumer Electronics, 2013

2011

Parallel pipelined array architectures for real-time histogram computation in consumer devices.

José O. Cadenas, Robert Simon Sherratt, Pablo Huerta, Wen-Chung Kao

IEEE Trans. Consumer Electron., 2011

2010

A double data rate architecture for OFDM based wireless consumer devices.

Robert Simon Sherratt, José O. Cadenas

IEEE Trans. Consumer Electron., 2010

2006

Verification and FPGA Circuits of a Block-2 Fast Path-Based Predictor.

Oswaldo Cadenas, Graham M. Megson

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005

A low clock frequency FFT core implementation for multiband full-rate ultra-wideband (UWB) receivers.

Robert Simon Sherratt, Oswaldo Cadenas, Nomita Goswami

IEEE Trans. Consumer Electron., 2005

A New Organization for a Perceptron-Based Branch Predictor and Its FPGA Implementation.

Oswaldo Cadenas, Graham M. Megson, Daniel Jones

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

FPGA Organization for the Fast Path-Based Neural Branch Predictor.

Oswaldo Cadenas, Graham M. Megson, Daniel Jones

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Implementation of a block based neural branch predictor.

Oswaldo Cadenas, Graham M. Megson, Daniel Jones

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004

A clocking technique for FPGA pipelined designs.

Oswaldo Cadenas, Graham M. Megson

J. Syst. Archit., 2004

A FPGA pipelined backward adaptive scalar quantizer.

Oswaldo Cadenas, Graham M. Megson

Proceedings of the Second IASTED International Conference on Circuits, 2004

2003

Pullpipelining: A technique for systolic pipelined circuits.

Oswaldo Cadenas, Graham M. Megson

Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

FPGA Circuits for a Monte-Carlo Based Matrix Inversion Architecture.

Oswaldo Cadenas, Graham M. Megson, Toomas P. Plaks

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003

2002

A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs.

Oswaldo Cadenas, Graham M. Megson

Proceedings of the Field-Programmable Logic and Applications, 2002

Improving mW/MHz Ratio in FPGAs Pipelined Designs.

Oswaldo Cadenas, Graham M. Megson

Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

2001

A n-Bit Reconfigurable Scalar Quantiser.

Oswaldo Cadenas, Graham M. Megson

Proceedings of the Field-Programmable Logic and Applications, 2001

Pipelining Considerations for an FPGA Case.

Oswaldo Cadenas, Graham M. Megson

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

1999

Experiences Using Reconfigurable FPGAs in Implementing Monte-Carlo Methods.

Toomas P. Plaks, Oswaldo Cadenas, Graham M. Megson

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999