Joseph Chong
Orcid: 0000-0002-4668-6357
According to our database1,
Joseph Chong
authored at least 5 papers
between 2014 and 2021.
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Bibliography
2021
Input-resistance reduced <i>g</i><sub><i>m</i></sub>-boosted common-gate transimpedance amplifier for 100 Gb/s optical communication.
Microelectron. J., 2021
A 0.13-<i>μ</i>m CMOS resonator-based frequency-doubling mechanism for clock recovery in a full-rate 40 Gb/s optical receiver.
Microelectron. J., 2021
2017
A full-rate 40 Gb/s clock and data recovery with resonator-based frequency-doubling mechanism in 0.13-μm CMOS.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
2015
A 100 Gb/s transimpedance amplifier with diode-connecting input-resistance-reduction in 32 nm CMOS technology.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
2014
A 100 Gb/s transimpedance amplifier in 65 nm CMOS technology for optical communications.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014