Juan A. López

According to our database1, Juan A. López authored at least 16 papers between 1999 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes.
J. Syst. Archit., 2014

Automated Data Flow Graph Partitioning for a Hierarchical Approach to Wordlength Optimization.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2012
Quantization of VLSI digital signal processing systems.
EURASIP J. Adv. Signal Process., 2012

2010
SQNR Estimation of Fixed-Point DSP Algorithms.
EURASIP J. Adv. Signal Process., 2010

Fast Fixed-Point Optimization of DSP Algorithms.
Proceedings of the VLSI-SoC: Forward-Looking Trends in IC and Systems Design, 2010

SQNR estimation of non-linear fixed-point algorithms.
Proceedings of the 18th European Signal Processing Conference, 2010

2009
Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs.
Int. J. Reconfigurable Comput., 2009

2008
Fast and accurate computation of the roundoff noise of linear time-invariant systems.
IET Circuits Devices Syst., 2008

Optimized Architectural Synthesis of Fixed-Point Datapaths.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

2007
Improved Interval-Based Characterization of Fixed-Point LTI Systems With Feedback Loops.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006
Optimized Synthesis of DSP Cores Combining Logic-based and Embedded FPGA Resources.
Proceedings of the International Symposium on System-on-Chip, 2006

High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2004
High-speed systolic array for gene matching.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Analysis of limit cycles by means of affine arithmetic computer-aided tests.
Proceedings of the 2004 12th European Signal Processing Conference, 2004

2003
Fast characterization of the noise bounds derived from coefficient and signal quantization.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

1999
Bit-Width Selection for Data-Path Implementations.
Proceedings of the 12th International Symposium on System Synthesis, 1999


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