Jun Yeon Won

According to our database, Jun Yeon Won authored at least 9 papers between 2016 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

FPGA-Only Implementation of MIPI C-PHY Receiver Using Blind Oversampling CDR for CMOS Image Sensors.

Jun Yeon Won, Shinki Jeong, Seongkwan Lee, Minho Kang, Insu Yang, Jaemoo Choi

Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2025

2024

Probe Card Ground Noise Canceling Circuit.

Seongkwan Lee, Minho Kang, Cheolmin Park, Jun Yeon Won, Jaemoo Choi, Chanyeol Park, Sunyong Park, Woonphil Yang

Proceedings of the IEEE International Test Conference, 2024

2023

Method for Diagnosing Channel Damage Using FPGA Transceiver.

Seongkwan Lee, Jun Yeon Won, Cheolmin Park, Minho Kang, Jaemoo Choi

Proceedings of the IEEE International Test Conference, 2023

Method for Adjusting Termination Resistance Using PMU in DC Test.

Seongkwan Lee, Minho Kang, Cheolmin Park, Jun Yeon Won, Jaemoo Choi

Proceedings of the IEEE International Test Conference, 2023

2022

4.5 Gsps MIPI D-PHY Receiver Circuit for Automatic Test Equipment.

Seongkwan Lee, Cheolmin Park, Minho Kang, Jun Yeon Won, HyungSun Ryu, Jaemoo Choi, Byunghyun Yim

Proceedings of the IEEE International Test Conference, 2022

2021

Development and Initial Results of a Brain PET Insert for Simultaneous 7-Tesla PET/MRI Using an FPGA-Only Signal Digitization Method.

Jun Yeon Won, Haewook Park, Seung-Eun Lee, Jeong-Whan Son, Yina Chung, Guen Bae Ko, Kyeong Yun Kim, Junghyun Song, Seongho Seo, Yeunchul Ryu, Jun-Young Chung, Jae Sung Lee

IEEE Trans. Medical Imaging, 2021

2018

Highly Integrated FPGA-Only Signal Digitization Method Using Single-Ended Memory Interface Input Receivers for Time-of-Flight PET Detectors.

Jun Yeon Won, Jae Sung Lee

IEEE Trans. Biomed. Circuits Syst., 2018

2016

Time-to-Digital Converter Using a Tuned-Delay Line Evaluated in 28-, 40-, and 45-nm FPGAs.

Jun Yeon Won, Jae Sung Lee

IEEE Trans. Instrum. Meas., 2016

Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA.

Jun Yeon Won, Sun Il Kwon, Hyun Suk Yoon, Guen Bae Ko, Jeong-Whan Son, Jae Sung Lee

IEEE Trans. Biomed. Circuits Syst., 2016