Junichi Hirase

According to our database, Junichi Hirase authored at least 16 papers between 1995 and 2014.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2014

Introduction of Yield Quadrant and Yield Capability Index for VLSI Manufacturing.

Junichi Hirase

IEICE Trans. Electron., 2014

Verification of Moore's Law Using Actual Semiconductor Production Data.

Junichi Hirase

IEICE Trans. Electron., 2014

2008

Defect Detection Rate through IDDQ for Production Testing.

Junichi Hirase

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2005

IDDQ Testing Method using a Scan Pattern for Production Testing.

Junichi Hirase, Yoshiyuki Goi, Yoshiyuki Tanaka

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Chip Identification using the Characteristic Dispersion of Transistor.

Junichi Hirase, Tatsuya Furukawa

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2003

Test Pattern Length Required to Reach the Desired Fault Coverage.

Junichi Hirase

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

High Precision Result Evaluation of VLSI.

Junichi Hirase

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Yield Increase of VLSI after Redundancy-Repairing.

Junichi Hirase

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Test Time Reduction through Minimum Execution of Tester-Hardware Setting Instructions.

Junichi Hirase

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Faster processing for microprocessor functional ATPG.

Junichi Hirase, Shinichi Yoshimura

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

Automatic Test Pattern Generation for Improving the Fault Coverage of Microprocessors.

Junichi Hirase, Shinichi Yoshimura, Tomohisa Sczaki

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

Scan Chain Diagnosis Using IDDQ Current Measurement.

Junichi Hirase, Naoki Shindou, Kouji Akahori

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

Economical Importance of the Maximum Chip Area.

Junichi Hirase

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1995

The Effect of CMOS VLSI IDDq Measurement on Defect Level.

Junichi Hirase, Masanori Hamada

IEICE Trans. Inf. Syst., 1995

Study on the Costs of On-site VLSI Testing.

Junichi Hirase

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Improvement of the Defect Level of Micro-computer LSI Testing.

Junichi Hirase

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995