Jürgen Hauenschild

According to our database, Jürgen Hauenschild authored at least 4 papers between 1990 and 1998.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

1998

PIN-preamp module and CDR-DMUX constituting a receiver for short-haul links up to 3.5 Gb/s.

Jürgen Hauenschild, Dirk Friedrich, Jürgen Herrle, Joachim Krug

IEEE J. Solid State Circuits, 1998

1996

A plastic packaged 10 Gb/s BiCMOS clock and data recovering 1: 4-demultiplexer with external VCO.

Jürgen Hauenschild, Claus Dorschky, Timo Winkler von Mohrenfels, Roland Seitz

IEEE J. Solid State Circuits, 1996

1991

A silicon bipolar decision circuit operating up to 15 Gb/s.

Jürgen Hauenschild, Hans-Martin Rein, William McFarland, D. Pettengill

IEEE J. Solid State Circuits, November, 1991

1990

Influence of transmission-line interconnections between gigabit-per-second ICs on time jitter and instabilities.

Jürgen Hauenschild, Hans-Martin Rein

IEEE J. Solid State Circuits, June, 1990