Kai-Chun Lin

According to our database, Kai-Chun Lin authored at least 8 papers between 2013 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Spectral Responsivity and Photoresponse Non-Uniformity of a Perimeter-Gated Single-Photon Avalanche Diode Imager.

Fahimeh Dehghandehnavi, Md. Sakibur Sajal, Kai-Chun Lin, Marc Dandin

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2022

Perimeter-Gated Single-Photon Avalanche Diode Imager with Vanishing Room Temperature Dark Count Probability.

Md. Sakibur Sajal, Kai-Chun Lin, Bathiya Senevirathna, Sheung Lu, Marc Dandin

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2016

A 50 nW-to-10 mW Output Power Tri-Mode Digital Buck Converter With Self-Tracking Zero Current Detection for Photovoltaic Energy Harvesting.

Po-Hung Chen, Chung-Shiang Wu, Kai-Chun Lin

IEEE J. Solid State Circuits, 2016

2015

20.10 A 50nW-to-10mW output power tri-mode digital buck converter with self-tracking zero current detection for photovoltaic energy harvesting.

Po-Hung Chen, Chung-Shiang Wu, Kai-Chun Lin

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications.

Chung-Shiang Wu, Kai-Chun Lin, Yi-Ping Kuo, Po-Hung Chen, Yuan-Hua Chu, Wei Hwang

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Schedule Management Application 'WiDay' Based on SAE Cloud Platform.

Shuang Ye, Chang-Dong Wang, Kai-Chun Lin, Xin-Yi Lin, Xuebo Liu, Han-Chen Yu

Proceedings of the Ninth International Conference on Frontier of Computer Science and Technology, 2015

2013

A 180 MHz direct access read 4.6Mb embedded flash in 90nm technology operating under wide range power supply from 2.1V to 3.6V.

Hung-Chang Yu, Ku-Feng Lin, Kai-Chun Lin, Yu-Der Chih, Sreedhar Natarajan

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology.

Hung-Chang Yu, Kai-Chun Lin, Ku-Feng Lin, Chin-Yi Huang, Yu-Der Chih, Tong-Chern Ong, Tsung-Yung Jonathan Chang, Sreedhar Natarajan, Luan C. Tran

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013