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Kaixuan Ye

Orcid: 0000-0002-8871-140X

According to our database1, Kaixuan Ye authored at least 4 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A Four-Channel TDM Clocked-Analog LDO Using a Shared Compensation Block for Thermo-Optic Tuning.
[BibTeX]
[DOI]
Tianchi Ye
,
Kaixuan Ye
,
Ziying Xie
,
Min Tan
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

2021
A Time-Division-Multiplexed Clocked-Analog Low-Dropout Regulator.
[BibTeX]
[DOI]
Ziying Xie
,
Kaixuan Ye
,
Ken Xingze Wang
,
Qixiang Cheng
,
Min Tan
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020
A 0.5-V Capless LDO With 30-dB PSRR at 10-kHz Using a Lightweight Local Generated Supply.
[BibTeX]
[DOI]
Chao Yang
,
Kaixuan Ye
,
Min Tan
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Four-Channel Clocked-Analog Time-Division Multiplexed LDO with Shared Compensation Capacitor for Thermal-Optic Phase Tuning.
[BibTeX]
[DOI]
Kaixuan Ye
,
Ziying Xie
,
Min Tan
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020


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